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AR# 69152

Design Advisory 2017.1 Tactical Patch for Vivado bi-directional logic issue using component mode primitives (IOBUF usage with IDDRE1, ISERDESE3, ODDRE1, OSERDESE3, or FDCE/FDPE/FDRE/FDSE with IOB=TRUE)

Description

Description

This issue affects UltraScale and UltraScale+ designs using component mode logic in bidirectional Mode in Vivado 2017.1.

For such designs, a tactical patch should be used to guarantee correct hardware functionality. Without the patch applied, designs can encounter hardware functionality or routing issues.

Symptoms

There are two different symptoms seen with this issue.

  1. Incorrect functionality in hardware
  2. A routing failure

Identification 

  1. Incorrect functionality in hardware is observed in designs that use Bidirectional I/O buffers (IOBUF type buffers and all derivatives) with the following component mode primitives: IFD (FDCE/FDPE/FDRE/FDSE with IOB=TRUE), IDDRE1 and ISERDESE3.
    The problem is observed in hardware when the outputs are 3-stated. Data for input logic (IFD, IDDRE1, and ISERDESE3) will be incorrectly driven by output logic (OFD, ODDRE1 and OSERDESE3) instead of the data from the input pin. This issue is not observed in simulations.
  2. A routing error is observed in designs that use Bidirectional I/O buffers (IOBUF type buffers and all derivatives) with the following component mode primitives: OFD (FDCE/FDPE/FDRE/FDSE with IOB=TRUE), ODDRE1 and OSERDESE3.
    The routing error message from Vivado is as shown below:

 

Checking all reachable nodes within 5 hops of driver and load

Unroute Type 1 : Site pin does not reach interconnect fabric
 Type 1 : HPIOB.I->SLICEL.F5
 -----Num Open nets: 1
 -----Representative Net: Net[12] spi_din_io_IOBUF_inst/O
 -----IOB_X2Y244/I -> SLICE_X96Y270/F5
 -----Driver Term: spi_din_io_IOBUF_inst/IBUFCTRL_INST/O Load Term [49]: uart_rx_o_OBUF_inst_i_1/I0
 Driver Pin does not reach Interconnect fabric within 5 hops.
 Expansion wavefront from Driver was blocked by locked nodes at level: 1
Phase 3.1 Initial Routing Verification | Checksum: 1d0be91f0

...

Phase 8 Verifying routed nets
CRITICAL WARNING: [Route 35-54] Net: spi_din_io_IOBUF_inst/O is not completely routed.
Resolution: Run report_route_status for more information.

 

Solution

A fix is targeted for the 2017.2 release. A tactical patch has been created to correct this behavior for the 2017.1 release.

  • Without the patch applied, the routing or functional issue will be seen.
  • With the patch applied, the routing and functional issue will be corrected.

Please note, that if a design checkpoint has been created with un-patched Vivado 2017.1, this will already contain the incorrect BITSLICE site programming.

With the patch applied, the BITSLICE site programming can be corrected by re-synthesizing.

Installation and usage information:

METHOD 1:

  1. Navigate to the $XILINX_VIVADO/patches directory (create this directory if it does not exist)
  2. Extract the contents of the ".zip" archive to a directory starting with the name AR69152
    Note: most extraction tools will allow you to automatically create a directory the same name as the zip file
  3. Run Vivado software tools from the original install location.


METHOD 2:

  1. Create a separate directory for the patched files
  2. Extract the contents of the ".zip" archive to the desired patch directory location
  3. Set the MYVIVADO environment variable to point to the Vivado directory under this patch directory
    For example:
    set MYVIVADO=C:\MYVIVADO\vivado-patch-AR69152\vivado\
  4. Run Vivado software tools from the original install location.

 

Attachments

Associated Attachments

Name File Size File Type
AR69152_vivado_2017_1_Lin_Win_preliminary_rev1.zip 14 MB ZIP
AR# 69152
Date 06/13/2017
Status Active
Type Design Advisory
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