This issue affects UltraScale and UltraScale+ designs using component mode logic in bidirectional Mode in Vivado 2017.1.
For such designs, a tactical patch should be used to guarantee correct hardware functionality. Without the patch applied, designs can encounter hardware functionality or routing issues.
There are two different symptoms seen with this issue.
A fix is targeted for the 2017.2 release. A tactical patch has been created to correct this behavior for the 2017.1 release.
Please note, that if a design checkpoint has been created with un-patched Vivado 2017.1, this will already contain the incorrect BITSLICE site programming.
With the patch applied, the BITSLICE site programming can be corrected by re-synthesizing.
Installation and usage information:
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