What is the behavior of a tandem PCIe based design when only state-1 bitstream is programmed and a TLP request is received?
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
There is a chance that TLP requests will be received, typically Vendor Defined Messages and Read Requests, when only stage-1 bitstream is programmed and before stage-2 is loaded.
The core returns unsupported requests (URs) for such requests.
If a Memory Write TLP is received with only stage-1 bitstream programmed, it will set the UR bit in the device status register.
Note: In some systems it has been observed that ERR_NONFATAL is being sent.
06/27/2017 - Initial Release