We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 69206

2017.1 - IBERT - RXOUTCLK frequency gets doubled when using IN-System IBERT core


When I include the In-System IBERT core to transceiver wizard IP in a design, the RXOUTCLK frequency gets doubled.

This behavior causes pulse width violations during implementation of the example design.


To work around this issue, use the 'set_case_analysis' XDC constraints with the value set to 0 on the 'rxrate_o' output port of In-System IBERT in the design top or targeted constraints file.

For example:

set_case_analysis 0 [get_pins gtwizard_ultrascale_0_in_system_ibert_0_inst/rxrate_o*].

This issue has been fixed in the 2017.4 release and later versions.

AR# 69206
Date 04/25/2018
Status Active
Type General Article
Page Bookmarked