In my design I configure the Display Port to dual lower.
I provide my own HDF, but the gtr_sel0 polarity is not set correctly by the device-tree generator, which results in the DisplayPort not coming up with Zynq UltraScale+ MPSoC evaluation boards.
In the 2017.1/2 release, the PetaLinux device-tree generator does not generate the right dual lane DisplayPort device-tree node.
To fix this issue follow the steps below:
1) Apply the attached patch to the device-tree recipe: <plnx-proj-root>/project-spec/meta-user/recipes-bsp/device-tree/device-tree-generation_%.bbappend
Note: To apply a patch to recipes, please refer to (UG1144) or http://www.wiki.xilinx.com/PetaLinux+Yocto+Tips
device-tree-generation_%.bbappend file content:
|Name||File Size||File Type|
|Boards & Kits||