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AR# 69251

2017.1/2 Vivado Simulator - ERROR: [XSIM 43-3316] Signal SIGSEGV received


My mixed language design is crashing during xelab data flow analysis:

Starting static elaboration
WARNING: [VRFC 10-278] actual bit length 2 differs from formal bit length 8 for port dmonout_cpl [/wrk/2016.4/nightly/2017_01_23_1756540/data/secureip/gthe4_channel/gthe4_channel_002.vp:26323]
Completed static elaboration
Starting simulation data flow analysis
ERROR: [XSIM 43-3316] Signal SIGSEGV received.


This can occur when a design contains hierarchical references in mixed language scenarios, which Vivado Simulator does not support.

This can be worked around by following the steps below:

  1. Change project language to VHDL
  2. Change simulator language from Mixed to VHDL or Verilog
  3. Reset all IP output products
  4. Generate output products, out of context per IP, and out of context per Block Design.

The issue is scheduled to be fixed in a future Vivado release.

AR# 69251
Date 06/20/2017
Status Active
Type Known Issues
  • Vivado Design Suite - 2017.1
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