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AR# 69252

2017.1/2 - compile_simlib passes incorrect switch to SecureIP compilation targetting Active HDL


When I compile simulation libraries for Active HDL, it fails with the following error:

ERROR: [Vivado 12-3591] compile_simlib failed to compile for active_hdl with 1 errors

When I check the generated .cxl.active_hdl.nt64.cmd file, an incorrect switch -sv is passed to the vlog command compiling SecureIP cells.


This issue will be fixed in Vivado 2017.3.

As a work-around, you can manually edit and run the command to compile the libraries.

For example:

C:\Aldec\Active-HDL-10.4-x64\BIN/vlog -sv2k12 -work secureip -f F:\XILINX_projects\project_11\project_3\project_3.cache\compile_simlib/secureip/.cxl.systemverilog.secureip.secureip.nt64.cmf
AR# 69252
Date 06/20/2017
Status Active
Type Known Issues
  • Vivado Design Suite - 2017.1
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