This answer record contains the Release Notes and Known Issues for the Virtex UltraScale+ HBM Controller and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2018.1 and newer tool versions.
HBM IP Page:
Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
Supported devices can be found in the following locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.
Table 1 correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
|HBM Version||Vivado Tools Version|
|v1.0 (Rev. 1)||2018.2|
|v1.0 (Rev. 2)||2018.3|
|v1.0 (Rev. 3)||2019.1|
For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the Internal Memory Interfaces section of the Memory Solutions page:
For the latest info on what's new for Vivado, including supported operating systems and IP release notes, see (UG973).
Known Issues and Resolved Issues
Table 2 provides the known and resolved issues for the Virtex UltraScale+ HBM Controller
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Table 2: Known and Resolved Issues
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 72608)||Virtex UltraScale+ HBM Controller - Configuration Error seen in Vivado Hardware Manager when HBM Stack Interface Rate is Less than 900MHz||v1.0 (Rev. 3)||Not Resolved|
|(Xilinx Answer 72607)||Virtex UltraScale+ HBM Controller - Debug Hub Clock Sometimes Not Connected which Results in Error at Implementation or Not Enabled Status in Hardware Manager||v1.0 (Rev. 3)||Not Resolved|
|(Xilinx Answer 71895)||Virtex UltraScale+ HBM Controller - Memory File Modifications Required for Write DQ Parity to Work when Enabled in the IP||v1.0||v1.0 (Rev. 3)|
|(Xilinx Answer 71894)||Virtex UltraScale+ HBM Controller - DRAM_y_STAT_TEMP Port Behavior Change in 2018.3||v1.0 (Rev. 2)||N/A|
|(Xilinx Answer 71795)||Virtex UltraScale+ HBM Controller - Simulation Errors Seen when HBM Memory is Operating at Frequencies Other than 900MHz||v1.0 (Rev. 2)||Not Resolved|
|(Xilinx Answer 71312)||Virtex UltraScale+ HBM FPGA XCVU31P, XCVU33P, XCVU35P, XCVU37P ES983x A cross stack transaction can hang the inter-stack channels||v1.0||Not Resolved for ES Devices|
Issue Resolved in Production Devices
|(Xilinx Answer 71165)||Virtex UltraScale+ HBM Controller - Performance is low when only 1 AXI port is used in a 2 stack design||v1.0||v1.0 (Rev. 2)|
|(Xilinx Answer 71097)||Virtex UltraScale+ HBM - Example Design Simulation Issues with VCS, Questa Sim, or IES||v1.0||Not Resolved|
|(Xilinx Answer 70919)||Virtex UltraScale+ HBM Controller - Timing Violations on ARESET_N path||v1.0||v1.0 (Rev. 1)|
|(Xilinx Answer 70435)||Virtex UltraScale+ HBM Controller - AXI_RRESP Can Be Incorrect in Some Conditions||v1.0||N/A|
|04/09/2018||New IP in 2018.1|
|10/22/2018||Updated for 2018.3|
|12/10/2018||Updated description of AR#71097, added AR#71795|
|01/07/2019||Updated description of AR#71097, added AR#71894 and AR#71895|
|05/02/2019||Updated for 2019.1|
|07/30/2019||Added AR#72607 and AR#72608|