AR# 69267

Virtex UltraScale+ HBM Controller - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the Virtex UltraScale+ HBM Controller and includes the following:

  • General Information
  • Known Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2018.1 and newer tool versions.

HBM IP Page:

https://www.xilinx.com/products/intellectual-property/hbm.html

Xilinx Forums:

Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

Solution

General Information

Supported devices can be found in the following locations:

 

      Virtex UltraScale+ HBM Controller Page

A white paper on Virtex UltraScale+ HBM is available here:

https://www.xilinx.com/support/documentation/white_papers/wp485-hbm.pdf

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Table 1 correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

HBM VersionVivado Tools Version
v1.02018.1
v1.0 (Rev. 1)2018.2
v1.0 (Rev. 2)2018.3
v1.0 (Rev. 3)2019.1
v1.0 (Rev. 4)2019.1.1
v1.0 (Rev. 4)2019.1.2
v1.0 (Rev. 4)2019.1.3
v1.0 (Rev. 5)2019.2
v1.0 (Rev. 6)2019.2.1
v1.0 (Rev. 6)2019.2.2
v1.0 (Rev. 7)2020.1


For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the Internal Memory Interfaces section of the Memory Solutions page:

For the latest info on what's new for Vivado, including supported operating systems and IP release notes, see (UG973).

Known Issues and Resolved Issues

Table 2 provides the known and resolved issues for the Virtex UltraScale+ HBM Controller

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 2: Known and Resolved Issues

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 73712)Virtex UltraScale+ HBM Controller - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardwarev1.0N/A
(Xilinx Answer 73372)Virtex Ultrascale+ HBM Controller - VCS Simulator Generates Large Number of Core Generated Messages During HBM Simulationv1.0 (Rev. 3)N/A
(Xilinx Answer 73028)Virtex UltraScale+ HBM Controller - HBM Example Design with Synthesizable Traffic Generator In Random Mode Returns Data Compare Errorsv1.0 (Rev. 5)v1.0 (Rev. 5) Vivado 2019.2.1
(Xilinx Answer 72608)Virtex UltraScale+ HBM Controller - Configuration Error seen in Vivado Hardware Manager when HBM Stack Interface Rate is Less than 900MHzv1.0 (Rev. 3)v1.0 (Rev. 5)
(Xilinx Answer 72607)Virtex UltraScale+ HBM Controller - Debug Hub Clock Sometimes Not Connected which Results in Error at Implementation or Not Enabled Status in Hardware Managerv1.0 (Rev. 3)Not Resolved
(Xilinx Answer 71895)Virtex UltraScale+ HBM Controller - Memory File Modifications Required for Write DQ Parity to Work when Enabled in the IPv1.0v1.0 (Rev. 3)
(Xilinx Answer 71894)Virtex UltraScale+ HBM Controller - DRAM_y_STAT_TEMP Port Behavior Change in 2018.3v1.0 (Rev. 2)N/A
(Xilinx Answer 71795)Virtex UltraScale+ HBM Controller - Simulation Errors Seen when HBM Memory is Operating at Frequencies Other than 900MHzv1.0 (Rev. 2)Not Resolved
(Xilinx Answer 71312)Virtex UltraScale+ HBM FPGA XCVU31P, XCVU33P, XCVU35P, XCVU37P ES983x A cross stack transaction can hang the inter-stack channelsv1.0Not Resolved for ES Devices
Resolved in Production Devices
(Xilinx Answer 71165)Virtex UltraScale+ HBM Controller - Performance is low when only 1 AXI port is used in a 2 stack designv1.0v1.0 (Rev. 2)
(Xilinx Answer 71097)Virtex UltraScale+ HBM Controller - Simulation Issues with VCS, Questa Sim, or IES Simulatorsv1.0Not Resolved
(Xilinx Answer 70919)Virtex UltraScale+ HBM Controller - Timing Violations on ARESET_N pathv1.0v1.0 (Rev. 1)
(Xilinx Answer 70435)Virtex UltraScale+ HBM Controller - AXI_RRESP Can Be Incorrect in Some Conditionsv1.0N/A

Revision History:

04/09/2018New IP in 2018.1
08/29/2018Added 71312
10/22/2018Updated for 2018.3
12/10/2018Updated description of AR#71097, added AR#71795
01/07/2019Updated description of AR#71097, added AR#71894 and AR#71895
05/02/2019Updated for 2019.1
07/30/2019Added AR#72607 and AR#72608
10/20/2019Updated for 2019.2
11/01/2019Added AR#73028
11/11/2019Updated description of AR#71097
02/13/2020Added AR#73372
05/21/2020Added AR#73712; Updated for 2020.1

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
70919 Virtex UltraScale+ HBM Controller - Timing Violations on ARESET_N path N/A N/A
71097 Virtex UltraScale+ HBM Controller - Simulation Issues with VCS, Questa Sim, or IES Simulators N/A N/A
71165 Virtex UltraScale+ HBM Controller performance is low when only 1 AXI port is used in a 2 stack design N/A N/A
71312 Virtex UltraScale+ HBM FPGA XCVU31P, XCVU33P, XCVU35P, XCVU37P ES983x – A cross stack transaction can hang the inter-stack channels N/A N/A
71795 Virtex UltraScale+ HBM Controller - Simulation Errors Seen when HBM Memory is Operating at Frequencies Other than 900MHz N/A N/A
71894 Virtex UltraScale+ HBM Controller - DRAM_y_STAT_TEMP Port Behavior Change in 2018.3 version N/A N/A
71895 Virtex UltraScale+ HBM Controller - Memory File Modifications Required for Write DQ Parity to Work when Enabled in the IP N/A N/A
72607 Virtex UltraScale+ HBM Controller - Debug Hub Clock Sometimes Not Connected which Results in Error at Implementation or Not Enabled Status in Hardware Manager N/A N/A
72608 Virtex UltraScale+ HBM Controller - Configuration Error seen in Vivado Hardware Manager when HBM Stack Interface Rate is Less than 900 MHz N/A N/A
73028 Virtex UltraScale+ HBM Controller - HBM Example Design with Synthesizable Traffic Generator In Random Mode Returns Data Compare Errors N/A N/A
73372 Virtex UltraScale+ HBM Controller - VCS Simulator Generates Large Number of Core Generated Messages during HBM Simulation N/A N/A
73712 Virtex UltraScale+ HBM Controller - Locked IPs from Earlier Versions of Vivado when Brought in to Vivado 2020.1 or Later Will Encounter Errors During Implementation or in Hardware N/A N/A
AR# 69267
Date 06/10/2020
Status Active
Type Release Notes
Devices
Tools
IP