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AR# 69274

LogiCORE IP MIPI D-PHY v3.1, v3.1 (Rev. 1) and v4.0 (Rev. 1) - Why does the ulpsactivenot only assert for one clock period for the MIPI D-PHY RX?

Description

Why does the ulpsactivenot only assert for one clock period for the MIPI D-PHY RX?

According to the MIPI Specification, the ulpsactivenot should remain asserted until the source starts Mark-1.

Solution

This issue occurs in the Vivado 2017.2 and 2017.4 generated LogiCORE MIPI D-PHY.

This issue is fixed in Vivado 2017.3, and has been fixed in Vivado 2018.1 and later.

  • Vivado 2017.3 - This issue is resolved in the MIPI D-PHY in Vivado 2017.3.
  • Vivado 2017.4 - Users can download the MIPI D-PHY from (Xilinx Answer 70530) to work around this issue.
  • Vivado 2018.1 - This issue is resolved in the MIPI D-PHY in Vivado 2018.1 and later.

It is recommended to update to the latest version of the IP.

Linked Answer Records

Master Answer Records

AR# 69274
Date 04/24/2018
Status Active
Type General Article
Devices
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
  • Kintex UltraScale+
  • Virtex UltraScale+
IP
  • MIPI
  • MIPI D-PHY
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