AR# 69291
UltraScale+ MPSoC Memory IP - The SFVA625 package does not support PL Memory Interfaces
Description
Version Found: DDR4 v2.2, DDR3 v1.4, RLDRAM3 v1.4, QDRII+ v1.4, QDRIV v2.0, LPDDR3 v1.0
Version Resolved: See (Xilinx Answer 58435)
In Vivado 2017.1, PL Memory Interfaces are customizable for the SFVA625 package.
(DS925) Table 1-74, Note 1 specifies that the SFVA625/SBVA484 packages do not support PL memory interfaces.
Is this a bug?
Solution
Starting in Vivado 2017.2, PL Memory Interfaces are not supported in the SFVA625 package.
The support was mistakenly added in previous versions of Vivado.
When upgrading your IP to Vivado 2017.2 you will see the following in IP Status:
If you click on the recommendation "Part not supported in Upgrade IP" then you will be presented with the following message:
When Customizing a New PL Memory Interface in Vivado 2017.2, you will see the following in the IP Catalog:
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Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 58435 | MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions | N/A | N/A |
Associated Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 69040 | UltraScale/UltraScale+ LPDDR3 IP - Release Notes and Known Issues | N/A | N/A |
| AR# 69291 | |
|---|---|
| Date | 01/11/2018 |
| Status | Active |
| Type | Known Issues |
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| Tools | |
| IP | |