I am synthesizing and implementing my design in Vivado 2017.1 and it fails in opt_design.
It is reporting black boxes for the modules that seem to have been moved out of the hierarchy.
This same design synthesizes and implements without issues in Vivado 2016.4.
The problem appears to be related to conditional statements. I have modules that are actively used based on the value of a generic or parameter.For example, if the generic is true, the code will generate module A and if false, it will generate module B and "true" is the default value of the generic.
The design appears to implement without issue if the default value of the generic is used.
However, if a non-default value is used, I see a black box error for the module that should be generated (Module B in this example).
In Vivado 2017.1, the hierarchy parser was enhanced to evaluate conditional statements when building the hierarchy view and determining the compile order and which files should be sent to synthesis.
Unfortunately, the code is only using the default value of generics and parameters based on the current level of hierarchy.
Therefore if the use of a module is dependent on a non-default value, it will be filtered out of the compile list and not sent to synthesis even if the generic value is correctly being sent from a higher level module.
Synthesis will black-box the module and later implementation fails as the black-box cannot be resolved.
If the HDL does not specify a default value for the generic and the value of the generic was not passed from the higher level module, no module will be generated, as there is no default value.
In most cases, you can work around this issue by setting the "Hierarchy Update" option to "Automatic Update, Manual Compile Order".
To do this in a Tcl script use the following command:
set_property source_mgmt_mode DisplayOnly [current_project]
With this option, the hierarchy in the Vivado Hierarchy Source View will still be displayed based on the default value of generics and parameters, but all source files will be sent to synthesis where the synthesis compile will correctly determine the generic or parameter value and compile the required files.
There are three different ways to pass a generic / parameter value to the HDL that will all see this problem