AR# 69324

UltraScale+ MPSoC Memory IP - The SFVC784 package has incorrect data rates in PL Memory Interfaces

Description

Version Found: DDR4 v2.2, DDR3 v1.4, RLDRAM3 v1.4, QDRII+ v1.4, QDRIV v2.0, LPDDR3 v1.0

Version Resolved: See (Xilinx Answer 58435)

(DS925) v1.3 April 20, 2017 Table 74, shows valid data rates for various packages in the PL Memory Interfaces. 

The SFVC784 package is limited to one speed grade lower than All FFV packages and FBVB900 packages when run above 1600 Mb/s.


In Vivado 2017.1 and earlier releases, if the user selects a SVFC784 package and customizes a PL Memory Interface, the data rates are incorrect in the Customization GUI for the selected memory device. 

The data rates are the same as All FFV packages and FBVB900 packages.

Solution

In Vivado 2017.2, the issue has been corrected in the Customization GUI to reflect (DS925) Table 74.

The SFVC784 package is now limited to one speed grade lower than All FFV packages and FBVB900 packages when run above 1600 Mb/s.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A
AR# 69324
Date 01/11/2018
Status Active
Type Known Issues
Devices
Tools
IP