AR# 69367

2017.3 Can I use a Global Clock I/O clock port to drive both IDELAYE3 and BUFG simultaneously?


In UltraScale devices, a Global Clock I/O clock port is used to drive both IDELAYE3 and BUFG at the same time. 

Is this a valid connection?


This is a valid connection in hardware.

In Vivado 2017.2 and previous versions there was no DRC message and implementation completed without any warnings. 

Starting with Vivado 2017.3, the below DRC error message was added to report the unsupported connections, but it is incorrectly flagged for the IDELAYE3 and BUFG connection:

[DRC REQP-1945] IDELAYE3.IDATAIN connected to other loads check: The IDELAYE3 cell IDELAYE3_inst pin IDELAYE3_inst/IDATAIN attached to net clk_IBUF is also connected to other loads. This is not routable due to conflicting attributes for the net.

In Vivado 2017.3, the DRC might halt the implementation flow when using a GCIO that drives both an IDELAYE3 and global clock buffers (BUFG/BUFGCE/BUFGCTRL/BUFGCE_DIV). 

This is a valid topology and it is safe to downgrade or disable the REQP-1945 in this scenario.

Example command to downgrade the DRC:

set_property SEVERITY {Warning} [get_drc_checks REQP-1945]
Vivado Version DRC REQP-1945
2017.2 and prior Does not need to be downgraded
2017.3 Needs to be downgraded
2017.4 Does not need to be downgraded
2018.x Needs to be downgraded
2019.1 onwards Does not need to be downgraded
AR# 69367
Date 02/27/2019
Status Active
Type General Article
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