AR# 69421

DisplayPort RX Subsystem - 7 Series: The CPLL must be powered down when not in use


In some systems, the CPLL can go into an unknown state due to high current needs, when there is no reference clock available.

The CPLL will need to be powered down and powered up again to resume normal operation.

One cause for the high current need is that the CPLL can rail to the maximum frequency when there is no reference clock.

Given that the DisplayPort RX Subsystem requires the use of a generated clock from the DP159, there will be a period of time where the reference clock for the CPLL will not be there due to an unplug event.


The solution is the power down the CPLL when it is not in use and to power it back up once there is a stable reference clock.

The CPLL needs to be powered down when an unplug event occurs and powered up during the training state, when a stable reference clock is available.


Here are the steps required in the application software, using XAPP1271 as an example:

At the top of the unplug interrupt handler function, Dprx_InterruptHandlerUplug(), power down the CPLL by adding the following lines.

//Power down CPLL

XVphy_PowerDownGtPll(&VPhy_Instance, 0, XVPHY_CHANNEL_ID_CHA, (TRUE));

//Hold GTs in reset

XVphy_ResetGtPll(&VPhy_Instance, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX,(TRUE));


At the top of the PLL reset interrupt function, Dprx_InterruptHandlerPllReset(), power up the CPLL:

//Power up the CPLL

XVphy_PowerDownGtPll(&VPhy_Instance, 0, XVPHY_CHANNEL_ID_CHA, (FALSE));

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
65447 DisplayPort RX Subsystem - Release Notes and Known Issues for Vivado 2015.4 and newer tool versions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
59294 Design Advisory GT wizard - CPLL causes power spike on power up for 7 series GTs N/A N/A
AR# 69421
Date 08/28/2017
Status Active
Type General Article