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AR# 69438

UltraScale/UltraScale+ RLDRAM3 IP v1.4 - Vivado 2016.4 and 2017.x - Previously working interface now fails calibration at Write DQ/DM Deskew step

Description

Version Found: RLDRAM3 v1.4 (Rev 1,2 & 3)

Version Resolved: See (Xilinx Answer 69037)

Due to changes in the IP in 2016.4 and 2017.x Vivado tools, users of the RLDRAM3 controller could experience intermittent calibration failures on an interface that previously passed calibration.

Failures from this issue will only occur during DM DQ Deskew. The change is causing the logic to perform the deskew sanity check on bytes that have not been deskewed. 

Therefore, the issue would only arise during the sanity check stage.

Solution

Please use the attached patch if you are experiencing the above symptoms.

If that does not correct the issue, please contact Xilinx Technical Support.

Attachments

Associated Attachments

Name File Size File Type
AR69438_Vivado_2017_1_preliminary_rev1.zip 575 KB ZIP
AR# 69438
Date 12/19/2017
Status Active
Type Known Issues
Devices More Less
Tools
IP
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