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AR# 69453

UltraScale/UltraScale+ PCI Express Integrated Block - Hot Plug Support

Description

What are the requirements to implement Hot Plug in UltraScale/UltraScale+ PCI Express Integrated Block IPs?


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

Below are the general guidelines on Hot Plug support in UltraScale/UltraScale+ PCI Express Integrated Block IPs.

 

  1. As an endpoint, there are no special requirements a user needs to enable/configure to support Hot Plug.

  2. Hot plug in Root Port configuration requires a hot plug controller on the board.
    This is the users' responsibility to implement it and is not implemented in Xilinx IP.

  3. Hot plug support requires user interaction with the following three registers.
    The Slot Status Register and Slot Capabilities Register must be configured and updated by the user through the configuration management interface.
    The user software needs to write to the Slot Control Register based on the user actions.

 

 

  1. Slot Status Register
  2. Slot Capabilities Register
  3. Slot Control Register

 

  1. To update the Slot Status Register, the user gets the required information from the Hot Plug Controller on the board and feeds it to the FPGA.
    The user needs to take this information and use it to update the Slot Status Register through the configuration management interface.

  2. It is the users' responsibility to update the Slot Capabilities Register through the configuration management interface.
    This register cannot be configured in the core configuration GUI.

 

Please check the relevant section of the PCI Express Specification for the details on Hot Plug working mechanism.

Revision History:

08/15/2017 - Initial Release

AR# 69453
Date 08/18/2017
Status Active
Type General Article
Devices
  • Kintex UltraScale
Tools
  • Vivado Design Suite - 2017.1
IP
  • PCI-Express (PCIe)
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