This Answer Record contains answers to frequently asked questions regarding External FIFO Interface on GEM when DMA implementation is not required.
1) What do "dma_tx_end_tog" and "dma_tx_status_tog" signals do?
Is "dma_tx_end_tog" a pulse at the end of every packet? Or does the "toggle" mean changing the signal polarity?
The port dma_tx_end_tog is output from the PS to the PL. This signal is toggled by the PS every time after the frame has transmitted to the PL on the FIFO interface.
The port dma_tx_status_tog is input to the PS from the PL. After transmitting each frame on the FIFO interface, the PS expects an acknowledgement from the PL.
After reception of the current frame, PL logic should toggle this signal to acknowledge the status. It is not a pulse.
Here is an example of ILA capture:
2) Can "tx_r_status" change in cases other than Full Duplex only?
From the description in (UG1085), I understand the status could also change when used in Full-Duplex mode, in case of a "fifo_underrun" condition.
This is correct.
3) I would like to understand what is the source of *_to_pl_bufg clocks and when it will become active. By default these clocks are not present.
What should I do to activate these clocks? Is it enough to activate the external FIFO interface instead of the DMA engine in order to have these clocks up and running?
These clocks are driven by the PS. These clocks are present when external FIFO interface is enabled. Vivado by default does not define the clock on *_to_pl_bufg.
The user should manually define the 125 MHz clock on these pins to enable the timing engine.
In the GEM_CLK_CTRL (0xFF180308) register, * _RX_SRC_SEL and *_REF_SRC_SEL are expected to set to 1 if using GMII, and 0 if using RGMII.
*_FIFO_CLK_SEL is expected to set to 1 as it is recommended to connect _clk_to_pl_bufg back to _rx_clk_from_pl when using an external FIFO interface.