We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 69507

JESD204B (v7.0) - RXLPMEN values incorrect when shared logic in core is used


When using the "Shared logic in core" settings for the JESD204B v7.0 core (and later), RXLPMEN is seen to be set to 1 for lane 1 only and set to 0 for all other lanes.

This will cause the wrong equalization mode to be used on all lanes except lane 1 and potentially result in a failure to SYNC or an unstable link.


To work around this issue, first enable the "Additional transceiver control and status ports" on the PHY tab of the JESD204B core GUI to expose the additional transceiver ports.

Then drive all of the "gt_rxlpmen" input bits to 1 from outside the core.

This issue will be resolved in Vivado 2017.3, JESD204B core (v7.2).

AR# 69507
Date 08/03/2017
Status Active
Type General Article
  • JESD204
Page Bookmarked