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AR# 69508

JESD204 PHY (v3.1) - RXLPMEN values incorrect when neither AXI-Lite nor Transceiver Debug are enabled

Description

When using the JESD204 PHY (v3.1) or later, if you are not using the AXI-Lite interface or Transceiver Debug, RXLPMEN is set to 1 for lane 1 only and set to 0 for all other lanes.

This will cause the wrong equalization mode to be used on all lanes except lane 1 and can potentially result in a failure to SYNC or an unstable link.

Solution

To work around this issue, either

1) Enable the AXI-Lite interface which will correct the problem.

Or

2) Enable the "Additional transceiver control and status ports" in the JESD204 PHY core GUI to expose the additional transceiver ports. Then drive all of the "gt_rxlpmen" input bits to 1 from outside the core.


This issue will be resolved in the Vivado 2017.3 version of the JESD204 PHY (v4.0).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
61911 LogiCORE IP JESD204 PHY core - Release Notes and Known Issues N/A N/A
AR# 69508
Date 07/26/2017
Status Active
Type General Article
IP
  • JESD204
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