AR# 69531

LogiCORE MIPI D-PHY v3.1, MIPI CSI-2 Rx Subsystem v2.2 (Rev. 1) - Why do I get warning "ncelab: *dphy_ip/mipi_dphy.srcs/sources_1/ip/mipi_dphy_rx1/mipi_dphy_rx1_core.v,436|49): implicit wire has no fanin" on system_rst_in when simulating the MIPI DPHY RX?

Description

When I simulate the MIPI D-PHY RX or the MIPI CSI-2 RX Subsystem, why do I see the following warning?

ncelab: *W,CSINFI (/dphy_ip/mipi_dphy.srcs/sources_1/ip/mipi_dphy_rx1/mipi_dphy_rx1_core.v,436|49): implicit wire has no fanin
(:mipi_csi2_ui_tb:mipi_csi2_rx_slv1_inst:csi2_rx_top_wrp_slv1_inst:csi2_rx_top_slv1_inst.phy_wrapper.
mipi_dphy_rx1.slave_rx.system_rst_in).

Solution

This issue is resolved in the MIPI D-PHY Rx v4.0 and MIPI CSI-2 RX Subsystem v3.0 in Viavdo 2017.3 and later versions.

Users can safely ignore this warning when using the MIPI D-PHY RX. 

"system_rst_in" is only used in the MIPI D-PHY TX configuration.

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AR# 69531
Date 04/09/2018
Status Active
Type General Article
IP