AR# 69533

Zynq UltraScale+ MPSoC 2016.4 - 2017.2: How to get a USB2.0 Standard interface working with an MPSoC device in PetaLinux and Standalone OS

Description

This Answer Record describes how to get a USB 2.0 Standard interface working with an MPSoC device in a PetaLinux or Standalone OS in Vivado 2016.4 - 2017.2 tools.

Solution

Known Issues:

With Zynq UltraScale+ MPSoC, the USB interface has two USB 2.0/3.0 controllers (USB0 and USB1).

Both USB0 and USB1 can work in USB2.0 without USB3.0 external PHY hardware and updates to internal GTR settings in the SoC Processor Configuration Wizard (PCW).

To get a USB 2.0 standard interface working, it is not mandatory to have USB 3.0 Processor Configuration Wizard (PCW) IP settings enabled by Vivado software. 

This means that you can disable GTR if the physical USB 3.0 interface is not used for the USB0/1 interface.

In Vivado version 2016.4, 2017.1 and 2017.2, in the Processor Configuration Wizard (PCW) IP settings, USB2.0 does not work when USB3.0 GTR is disabled or is not selected from the PCW GUI.

This issue is related to the PIPE3 clock which gets disabled altogether for USB3.0 and USB2.0 by the Vivado software while exporting the hardware design (HDF) to SDK software.

This is a Vivado software settings issues and is fixed in the 2017.3 Vivado software release.

Work-around:

To work around this issue in Vivado 2016.4, 2017.1 and 2017.2, please follow the steps below:

Step 1:

Open Vivado and select the USB 2.0 interface in the Zynq UltraScale+ MPSoC IP wizard. Do not select USB 3.0.


 


Step 2

After generating the Bitstream, export the hardware definition file to SDK software.

Generate the SDK FSBL source code for the exported HDF file and then add the below source in to the function XFsbl_HookBeforeHandoff:

XFsbl_Out32 (0XFE20C200, 0x02417); /* USB3_0_XHCI_GUSB2PHYCFG_OFFSET= 0XFE20C200*/

XFsbl_Out32 (0xFF9D007C, 0x1); /*disable usb3.0 pipe3 clock and enable usb2.0 clock

XFsbl_Out32 (0xFF9D0080, 0x1); /*Pipe power present*/

XFsbl_Out32 (0xff5e00a8, 0x01000602); /*LPD switch to active the clock*/


Note: the ULPI PHY RESETB signal is not a part of USB SoC, so the user needs to manage it from their side. RESETB can be a part of MIO or EMIO or GPIO. 

Please make sure it gets released in the FSBL or U-BOOT stage to function properly on the Linux OS side.

If this is done from the FSBL side, then the appropriate code should be mentioned in the XFsbl_HookBeforeHandoff function.

For Example, with a ZCU102, I have used the MODE_1 configuration signal logical ANDed with the PS_POR_B signal. 

This source code can be seen in the file "xfsbl_board.c"

See (UG1087):

https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html


Step 3: PetaLinux OS settings.

Disable SERDES in DT (system-user.dtsi) and use the same mode as the USB mode, Peripheral or Host.

* If USB0 is used for peripheral use, then the DT will look like the following:

&dwc3_0 {

  status = "okay";

  dr_mode = "peripheral";

  snps,dis_u2_susphy_quirk;

  snps,dis_u3_susphy_quirk;

  maximum-speed = "high-speed";

} ;

&usb0 {

    status = "okay";

    /delete-property/clocks;

    /delete-property/clock-names;

    clocks = <0x3 0x20>;

    clock-names = "bus_clk";

};

 

&serdes{

 status = "disabled";

};

AR# 69533
Date 03/16/2018
Status Active
Type Known Issues
Devices