AR# 69568

50G Ethernet Subsystem - 2017.1 and earlier - Incorrect Alignment Marker Spacing used if generating core with RS-FEC, but not enabling RS-FEC

Description

The 50G specification calls for different alignment marker spacing to be used if the RS-FEC is enabled.

In Vivado 2017.1 and earlier, if you are not using the AXI-Lite Register Interface, the alignment marker spacing is tied off to always have the 50G RS-FEC alignment marker spacing (16'4FFF) if the core is generate with RS-FEC.

This will cause link-up problems with third party devices when the core is generated with RS-FEC, but the RS-FEC is not enabled.

  1. When the 50G RS-FEC is enabled, the alignment marking spacing should be ctl_rx/ctl_tx_vl_length_minus1 = 16'4FFF;
  2. When the 50G RS-FEC is NOT enabled, the alignment marking spacing should be ctl_rx/ctl_tx_vl_length_minus1 = 16'3FFF;

Solution

In Vivado 2017.2 and later versions, the 50G Ethernet core configuration vector interface has been updated to change the alignment marker spacing depending on whether RS-FEC is enabled or disabled.

If using the AXI-Lite Register interface, you will need to write to the ctl_rx/ctl_tx_vl_length_minus1 register to change the length.

AR# 69568
Date 08/01/2017
Status Active
Type General Article
Devices
Tools
IP