General Description: The CLKDV output always divides the input clock value by 2, regardless of the value of the CLKDV_DIVIDE attribute.
The Foundation Logic Simulator is not capable of accepting attributes. Because the CLKDLL is a primitive that requires an attribute to determine the output value, the value can only be set to a default setting. Therefore, the CLKDV_DIVIDE attribute will always use the default value of 2. This means that the CLKDV output should always be one-half the frequency of CLK0.
The other functions of the various DLL components (2x, phase shift, etc...) may be simulated in timing simulation. The CLKDV_DIVIDE attribute is applied correctly to the physical design, but it is ignored during timing simulation. The only way to work around this issue within the Foundation Logic Simulator is to stimulate the net driven by the CLKDV pin with the desired frequency.
Other third party simulation tools, including ModelSim, should correctly simulate the CLKDV function.