This answer record contains patch updates for the MIPI D-PHY LogiCORE IP v3.1 (Rev. 1)
This patch fixes the following issue in the LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) generated from the Vivado 2017.2 design tools.
|(Xilinx Answer 69671)||When using 7 Series Devices to implement MIPI D-PHY TX, why do we see overshoot on the output signal during HS-->LP transmission?|
|(Xilinx Answer 69931)||When using MIPI D-PHY TX, why is the HS-PREPARE length violating MIPI D-PHY specification version 1.1?|
|(Xilinx Answer 69766)||When using MIPI D-PHY TX, why do we have skewed SoT signal between lanes?|
See the individual Answer Record for details on which release the issue is fixed in.
Install the patch as per the instructions in the included README.txt file to resolve this issue.
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