AR# 69760

2017.2 LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) - Patch Updates for the MIPI D-PHY LogiCORE IP v3.1 (Rev. 1)

Description

This answer record contains patch updates for the MIPI D-PHY LogiCORE IP v3.1 (Rev. 1)

Solution

This patch fixes the following issue in the LogiCORE IP MIPI D-PHY v3.1 (Rev. 1) generated from the Vivado 2017.2 design tools.

(Xilinx Answer 69671)When using 7 Series Devices to implement MIPI D-PHY TX, why do we see overshoot on the output signal during HS-->LP transmission?
(Xilinx Answer 69931)When using MIPI D-PHY TX, why is the HS-PREPARE length violating MIPI D-PHY specification version 1.1?
(Xilinx Answer 69766)When using MIPI D-PHY TX, why do we have skewed SoT signal between lanes?


See the individual Answer Record for details on which release the issue is fixed in.

Patch Installation:

Install the patch as per the instructions in the included README.txt file to resolve this issue.

Attachments

Associated Attachments

Name File Size File Type
AR69760_Vivado_2017_2_preliminary_rev1.zip 1 MB ZIP

Linked Answer Records

Master Answer Records

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Associated Answer Records

AR# 69760
Date 04/24/2018
Status Active
Type General Article
Devices More Less
Tools
IP