This occurs when a VPLL output clock is shared with multiple peripherals, especially DP_VIDEO and TOPSW_MAIN in a Vivado design.
To resolve this issue, set TOPSW_MAIN to DPLL and DP_VIDEO to VPLL.
Note: VPLL should be used only for Display Port (DP_VIDEO)
AR# 69764 | |
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Date | 10/06/2017 |
Status | Active |
Type | General Article |
Devices | |
Tools | |
Boards & Kits |