When using the MIPI D-PHY v3.1 (Rev.1) Transmitter side, there can be too much skew on the SoT signal between lanes.
This can cause errors at the MIPI receiver. This behavior varies depending on implementation results.
This issue occurs in the MIPI D-PHY (Transmitter side) generated from:
According to the MIPI D-PHY specification version 1-1, the MIPI D-PHY transmitter output signal must have no more than +/-3.5 UI skew between lanes.
However, as a result of this issue, after implementation of the MIPI D-PHY TX, it can have skew between lanes of up to +/- 8UI.
Users should update to the latest version of the IP.
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