The Vivado IP Integrator GUI is used to configure the QSPI reference clock, which is the clock to the internal QSPI controller in the Zynq UltraScale+ MPSoC.
How do I set the QSPI device frequency?
To set the external QSPI device clock, there is a divider that is set in the FSBL in xfsbl_qspi.c.
The pre-scaler divider uses the QSPI reference clock as a source and the range of divider values are defined in xqspipsu.h. Values range from divide by 2 to divide by 256.
The default divider in xfsbl_qspi.c is XQSPIPSU_CLK_PRESCALE_8, which is a divide by 8.
The default QSPI device clock is 200 MHz, and the default FSBL will provide a QSPI device clock of 25 MHz.
If a faster QSPI device clock is desired, please make sure that all QSPI connection guidelines are followed as described in (UG1085) and (UG583).