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AR# 69846

2017.2 Vivado - The hierarchy source view in Vivado 2017.x is incorrect or takes a long time to update compared with Vivado 2016.x

Description

I am seeing multiple issues with the Hierarchy Source View (HSV) in Vivado 2017.x.

  • The correct hierarchy is not being shown
  • Each time I add or update a source file, the Sources Tab displays an "Updating" status and I have to wait several minutes for it to finish.  Looking at the system processes, I see that srcscanner (.exe) is using a lot of the processor resources.
  • My HDL files are placed in a "Non-Module" category instead of within the hierarchy

Solution

In Vivado 2017.1 the engine that generates the hierarchy data displayed on HSV tab was updated.  In order to create the needed data, Vivado launches an executable named srcscanner.exe.

If the source scanner is unable to parse the file for any reason, the file will be listed under the Non-module folder.

Srcscanner typically exhibits a runtime issue when it hits a code construct it does not like or understand.  There have been some reported cases where srcscanner is not recognizing valid HDL code.  

If you suspect this is the case, please submit the example code or project for evaluation and fix if needed.

HSV has a few operating modes that go from fully automatic (default ) to fully manual.

  • Automatic update and Compile Order
  • Automatic update, Manual Compile Order
  • No Update, Manual Compile Order

Most issues with slowness or incorrect file compile order being sent to synthesis can be worked around by using one of the manual compile order settings.  

This can be done in the GUI by right clicking in the HSV and selecting the desired option under Hierarchy Updates or by running the equivalent Tcl command in the Tcl console:

set_property source_mgmt_mode DisplayOnly [current_project]
set_property source_mgmt_mode None [current_project]


When using either of the Manual modes, Vivado will send all of the files in the source fileset to the Synthesis (or Simulation) process being run and the Synthesis process will do a separate parse of the files to determine dependencies.

In Vivado 2017.3, extra messaging will be added to the scrscanner.  However, users might find better syntax related messaging if they run the synthesis and/or simulation process.

Below are some known causes for srcscanner to hang, freeze or give an exception.

  • Having an input to a function with an undefined type that is used as a denominator in an equation. When the function does not specify the type of input arguments, the default type is bit, so it is taking it as 0, resulting in a divide by zero.

For Example: The function get_width has two inputs with undefined type:

function integer get_width;
    input area;
    input base;

This results in a divide by zero operation at "width = (area/base);".

There is no problem if the type is defined as "integer".

function integer get_area;
    input integer area;
    input integer base;

  • Having a VHDL attribute specification for labeled statements where its value is an uninitialized generic. (Fixed in Vivado 2017.2)
AR# 69846
Date 11/06/2017
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2017.2
  • Vivado Design Suite - 2017.1
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