General Description: When library elements are instantiated in an HDL design, Foundation Express issues the following warning:
Cannot link cell 'M2_1/$1I9' to its reference design 'AND2'. (FPGA-LINK-2).
These may be instantiated in the HDL source by the user, or may be added to a schematic that is subsequently exported to HDL for synthesis.
If the instantiated components are library primitives, then these unlinked cells can be ignored; NGDBUILD (Translate) will insert these components into the netlist. However, library macros must not be instantiated in your HDL code for Virtex designs, as the underlying description of how the macro is constructed is not available in the HDL Flow. NGDBUILD will give an "Unexpanded Block" error if it does not recognize the component instantiated in the design.
If the design is built with a top level schematic, the best solution is to use the Schematic Flow, not the HDL flow. FPGA Express does not have access to Virtex library primitives (combinatorial logic is built with LUTs instead).