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AR# 6987

Foundation Express: Virtex unified library macros/primitives not recognized in HDL flow


Keywords: HDL Flow, Schematic Top Level, Unlinked Cells, Express, Virtex, F2.1i, Verilog, VHDL

Urgency: Standard

General Description: When library elements are instantiated in an HDL design, Foundation Express
issues the following warning:

Cannot link cell 'M2_1/$1I9' to its reference design 'AND2'. (FPGA-LINK-2).

These may be instantiated in the HDL source by the user, or may be added to a schematic that is
subsequently exported to HDL for synthesis.



If the instantiated components are library primitives, then these unlinked cells can be ignored;
NGDBUILD (Translate) will insert these components into the netlist. However, library macros
must not be instantiated in your HDL code for Virtex designs, as the underlying description of
how the macro is constructed is not available in the HDL Flow. NGDBUILD will give an
"Unexpanded Block" error if it does not recognize the component instantiated in the design.


If the design is built with a top level schematic, the best solution is to use the Schematic Flow,
not the HDL flow. FPGA Express does not have access to Virtex library primitives (combinatorial
logic is built with LUTs instead).
AR# 6987
Date 06/13/2002
Status Archive
Type General Article