AR# 69881

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JESD204 Solution Center - Design Assistant - Simulation

Description

This Answer Record forms part of the JESD204 Solution Center, and covers JESD204 Simulation settings and information.

Solution

(Xilinx Answer 63368)	JESD204 - What simulation timescale is used in the JESD example design testbench?
(Xilinx Answer 65479)	JESD204B - Single Lane JESD204 Transmit Example Design Simulations Timing Out When Using QuestaSim
(Xilinx Answer 67349)	JESD204B v7.0 - TX Lane ID is incorrect in ILA sequence, also resulting in possible Example Design simulation failure

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
67695	JESD204 - Design Assistant	N/A	N/A

Child Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
63368	JESD204 - What simulation timescale is used in the JESD example design testbench?	N/A	N/A
65479	JESD204B - Single Lane JESD204 Transmit Example Design Simulations Timing Out When Using QuestaSim	N/A	N/A
67349	JESD204B v7.0 - TX Lane ID is incorrect in ILA sequence, also resulting in possible Example Design simulation failure	N/A	N/A

AR# 69881
Date	10/25/2017
Status	Active
Type	Solution Center
IP	JESD204

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