AR# 69926


Zynq UltraScale+ MPSoC Controller for PCI Express (Vivado 2017.2) - Speed and Link Width status in Link Status Register


When the PS-PCIe core is configured as Root Port and there is no endpoint connected, the link status register in the LSPCI report shows Gen1x1 instead of Gen1x0.


The link status bits for link speed and link width are undefined when the link is not established. 

The bits are valid only after the link is up.

Revision History:

10/23/2017: Initial Release

AR# 69926
Date 10/23/2017
Status Active
Type General Article
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