AR# 69947

UltraScale Memory IP designs giving hold violations

Description

Version Found: DDR4 v2.2 (Rev. 1), DDR3 v1.4 (Rev. 1), RLDRAM3 v1.4 (Rev. 1), QDRII+ v1.4 (Rev. 1), QDRIV v2.0 (Rev. 1), LPDDR3 v1.0 (Rev. 1)

Version Resolved: See (Xilinx Answer 58435)

3 out of 600 builds give hold violations.

Solution

If you encounter this issue, you can try to reimplement, change implementation strategy, or use a Pblock around the memory IP.

If you are unable to close timing please open a Service Request with Xilinx support.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A
AR# 69947
Date 12/20/2017
Status Active
Type Known Issues
Devices
IP More Less