Version Found: DDR4 v2.2 (Rev. 1), DDR3 v1.4 (Rev. 1), RLDRAM3 v1.4 (Rev. 1), QDRII+ v1.4 (Rev. 1), QDRIV v2.0 (Rev. 1), LPDDR3 v1.0 (Rev. 1)
Version Resolved: See (Xilinx Answer 58435)
3 out of 600 builds give hold violations.
If you encounter this issue, you can try to reimplement, change implementation strategy, or use a Pblock around the memory IP.
If you are unable to close timing please open a Service Request with Xilinx support.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 58435 | UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues | N/A | N/A |