The JESD204 PHY v3.4 and v4.0 include the CPLL_CAL block.
Use of this block means that the P_USE_CPLL_CAL parameter on the GT reset block is set to 1.
When this change is made, the 2 us delay on the signals driving cpllpd_in is no longer present (CPLL reset becomes unreliable).
This affects UltraScale and UltraScale+ designs only.
To ensure that the timing requirement is met on the CPLLPD pin, it is recommended to enable the AXI4-Lite interface on the core and hold register 0x408 high for at least 2 us when a reset of the CPLL is required.
If the JESD204 PHY is being used as part of the JESD204 IP (JESD204 has been generated with Shared Logic in the core) it is recommended to generate the JESD204 IP with "Shared Logic in Example Design" and then generate the JESD204 PHY separately and include the AXI4-Lite interface.
This will allow access to register 0x408.
This issue will be resolved in Vivado 2017.4.