After upgrading a design to Vivado 2017.3, when changing the clock frequency of a PS AXI interface, the following warning can occur.
How do I resolve it?
To work around this issue after an upgrade to Vivado 2017.3, the PS block can be replaced.
This can be accomplished by parameterizing a new PS block and then using the following Tcl command to swap the IP instances without having to reconnect interfaces:
replace_bd_cell old_instname new_instname
Alternatively, to avoid this issue you can apply the patch in (Xilinx Answer 69960) to Vivado 2017.3 before upgrading a previous design.
This upgrade issue will be fixed starting in Vivado 2017.4.