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AR# 70041

LogiCORE IP SMPTE SD/HD/3G-SDI (SMPTE SDI) v3.0 - IP Latency Information SMPTE SDI IP in 3G-SDI mode

Description

(PG071) does not mention IP latency information for SMPTE SD/HD/3G-SDI TX/RX IP in 3G-SDI mode.

Solution

IP Latency Information for SMPTE SD/HD/3G-SDI IP in 3G-SDI mode is described in this Answer Record.

The native SDI TX input stream to SDI TX IP output == 17 clock cycles of tx_usrclk
The RX SDI IP input to Native RX SDI data stream output == 21 clock cycles of rx_usrclk

Please note that this latency information:

  1. Does not include transceiver part latency
  2. Assumes that the SDI IP is already locked

 

This Answer Record will be removed after this latency information is updated in (PG071).

 

Linked Answer Records

Master Answer Records

AR# 70041
Date 01/15/2018
Status Active
Type General Article
Tools
IP
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