(PG071) does not mention IP latency information for SMPTE SD/HD/3G-SDI TX/RX IP in 3G-SDI mode.
IP Latency Information for SMPTE SD/HD/3G-SDI IP in 3G-SDI mode is described in this Answer Record.
The native SDI TX input stream to SDI TX IP output == 17 clock cycles of tx_usrclk
The RX SDI IP input to Native RX SDI data stream output == 21 clock cycles of rx_usrclk
Please note that this latency information:
This Answer Record will be removed after this latency information is updated in (PG071).