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AR# 70061

UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2017.3) - PIPE Simulation fails when PIPELINE STAGE of 2 is enabled

Description

Version Found: v4.4

Version Resolved and other Known Issues: See (Xilinx 57945)

When simulating the UltraScale FPGA Gen3 Integrated Block for PCI Express core example design with PIPELINE STAGE set to '2', the simulation fails.

Solution

This is a known issue to be fixed in a future release of the core.

Separate patches have been provided to fix the issue in Vivado 2017.1 and Vivado 2017.3 respectively.

For instruction on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

11/01/2017 - Initial Release

Attachments

Associated Attachments

AR# 70061
Date 11/01/2017
Status Active
Type Known Issues
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)
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