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AR# 70065

2017.3 Zynq-7000 SoC, Zynq UltraScale+ MPSoC: Vivado Hardware Manager might fail to program the bitstream


The programming of the bitstream in Zynq-7000 or Zynq UltraScale+ MPSoC using 2017.3 Vivado Hardware Manager can fail because the tool is not driving the internal PROG_B prior to programming.

This can happened if the device is NOT booted in JTAG boot mode or if the internal PROG_B is asserted (for example due to a failed boot or a software setting), or if the user is re-programming the bitstream for the second time.

The internal PROG_B signals are:

Zynq UltraScale+ MPSoC:

CSU.pcap_prog{pcfg_prog_b} = 0 (PL in reset)


DEVCFG.CTRL{pcfg_prog_b} = 0 (It acts as the PROG_B signal in the PL)


The attached patch will ensure that the tool does toggle the internal PROG_B before programming the bitstream.


Associated Attachments

Name File Size File Type
AR70065_vivado_2017_3_preliminary_rev1.zip 13 MB ZIP
AR# 70065
Date 05/25/2018
Status Active
Type Known Issues
  • Zynq UltraScale+ MPSoC
  • Zynq-7000
  • Vivado Design Suite - 2017.3
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