UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 70065

2017.3 Zynq-7000 SoC, Zynq UltraScale+ MPSoC: Vivado Hardware Manager might fail to program the bitstream

Description

The programming of the bitstream in Zynq-7000 or Zynq UltraScale+ MPSoC using 2017.3 Vivado Hardware Manager can fail because the tool is not driving the internal PROG_B prior to programming.

This can happened if the device is NOT booted in JTAG boot mode or if the internal PROG_B is asserted (for example due to a failed boot or a software setting), or if the user is re-programming the bitstream for the second time.

The internal PROG_B signals are:

Zynq UltraScale+ MPSoC:

CSU.pcap_prog{pcfg_prog_b} = 0 (PL in reset)

Zynq-7000:

DEVCFG.CTRL{pcfg_prog_b} = 0 (It acts as the PROG_B signal in the PL)

Solution

The attached patch will ensure that the tool does toggle the internal PROG_B before programming the bitstream.

Attachments

Associated Attachments

Name File Size File Type
AR70065_vivado_2017_3_preliminary_rev1.zip 13 MB ZIP
AR# 70065
Date 05/25/2018
Status Active
Type Known Issues
Devices
  • Zynq UltraScale+ MPSoC
  • Zynq-7000
Tools
  • Vivado Design Suite - 2017.3
Page Bookmarked