General Description: The following error may be seen in map on designs created by FPGA Express:
ERROR:baste:26 - The TBUFs "C8540" and "C8698" drive the same output signal "DATAOUT<31>", and are enabled by the same enable signal "N6145". This means that both TBUFs will drive the signal "DATAOUT<31>" when the enable signal "N6145" is active.
Check your HDL code.
If FPGA Express sees that three-state buffer enable pins are never enabled, it will simply tie the T pin of the BUFT to VCC. The BUFT will never be able to drive a signal but will remain in the netlist. If multiple TBUFs are disabled in this way, MAP will issue an error because it sees that the T pins are all sourced by the same signal (even though it is VCC), and will assume potential contention.
The solution to this issue is to eliminate the three-state inferences that will never be active. In the MAP error message, the names of the TBUFs and the name of the VCC signal will be meaningless, but the name of the signal it drives will point you to the proper three-state inferences.