I have a block Design (BD) in my project that contains module references.
In Vivado 2016.4 the project compiles without error. However, when I open the same project in Vivado 2017.1 and run report_ip_status, I see that the module reference IPs are stale and need to be refreshed (There is a refresh changed modules banner at the top).
Nothing in my HDL has changed, so why are the Module reference IPs stale?
This is due to a change to the Vivado hierarchy source view (HSV) parser between Vivado 2016.4 and Vivado 2017.1.
The Vivado 2017.1 HSV parser is returning files in a different order compared to previous versions.
Going forward HSV2.0 will return files in a deterministic manner.
The staleness of a modref is determined by the contents of the files it references.
The content is determined by doing a checksum across all of the files passed to it from the flows.
If the order of files presented to the code changes, the overall CRC will change.
Checks have been established in the new parser to ensure that the file order be deterministic as far as possible so that this issue should not occur when migrating to future Vivado versions.