' not found" when synthesizing BD with VHDL target language">


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AR# 70082

2017.2 Vivado IP Flows - Synthesis gives "ERROR : module '' not found" when synthesizing BD with VHDL target language


I have a block design (BD) that is giving an error when I generate the output product using either out of context (OOC) per IP or OOC per BD.

ERROR : module 'bd_smart_connect_0' not found
: failed synthesizing module design_1_axi_smc_0'


An issue was found in Vivado 2017.2, which affects SmartConnect and system_ila IP cores in a BD if the project target language is changed.

Root cause:

  • The IP is created in a project with a particular language (for example, Verilog)
  • The language for the project is changed to VHDL.
  • Deferred Elaboration is then executed. The IP is elaborated with 'Verilog' used as part of its stale-ness check.
  • Generation is invoked.
  • Generation notices the discrepancy between the current 'VHDL' project setting and the desired 'Verilog' project setting.
    It attempts to customize and elaborate the IP before generation.
  • Because the IP is a deferred Elaboration IP, the elaborate call does 'unelaborate' but does not subsequently re-elaborate.

This issue is fixed in Vivado 2017.3.

To work around the issue in Vivado 2017.2, a user can do one of the following.

  • Generate the target language which was originally used for the project
  • Use the global synthesis option when generating the output products for the BD
  • First generate the output products using the global synthesis option and then generate again using OOC per IP or OOC per BD
AR# 70082
Date 12/04/2017
Status Active
Type Known Issues
  • Vivado Design Suite - 2017.2
  • Vivado Design Suite - 2017.1
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