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AR# 70148

2017.3 Zynq-7000 SoC: QSPI flash programming now requires that you specify an FSBL

Description

Starting with the 2017.3 release, Vivado Hardware Manager and XSDK require that you specify an FSBL in order to program a QSPI flash.

This has been done in order to have a common flow between Zynq-7000 and Zynq UltraScale+.

Solution

With this change there are a number of implications:

1) The user needs a working FSBL.

If this FSBL is initializing DDR, then DDR needs to be functioning even if the QSPI flash programming does not really use it.

A suggestion is to use #define FSBL_DEBUG_INFO in the FSBL, to check if the UART of the FSBL is fully executed without hangs during QSPI flash programming.


2) If you have issues programming the FLASH in Vivado 2017.3 or 2017.4, add the following environment variable.

(The ENV variable is not required for 2018.1):

XIL_CSE_ZYNQ_UBOOT_QSPI_FREQ_HZ = 10000000

This will force the mini-uBoot to set the QSPI device clock to 10 MHz. 

Note: depending on your FSBL design, you might see a different QSPI clock on your hardware.


3) The device clocking is now configured by the FSBL rather than the tool.

The configuration which was previously used by the tool is listed below. 

If you have issues programming the flash, you should check the FSBL configuration against this table.

Register NameRegister AddressRegister Value
ARM_PLL_CFG0xF80001100x00177EA0(default values)
ARM_PLL_CTRL0xF80001000x0001A000ARM_PLL = 866 MHz (not bypassed)
ARM_CLK_CTRL0xF80001200x1F000400CPU_6x4x = 866 / 4 = 216 MHz
IO_PLL_CFG0xF80001180x00177EA0(default values)
IO_PLL_CTRL0xF80001080x0001A000IO_PLL = 866 MHz (not bypassed)
PLL_STATUS0xF800010C0x0000003FARM_PLL and IO_PLL are LOCKED and STABLE.

* Assuming PS_REF_CLK = 33.33 MHz


4) In case of XIP (Execute in place from QSPI), a custom FSBL that executes from OCM needs to be created to be specified during QSPI flash programming.

 

AR# 70148
Date 05/25/2018
Status Active
Type General Article
Devices
Tools
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