AR# 70196


LogiCORE IP MIPI D-PHY v4.0 - On 7 Series Devices, High-Speed Lanes are unconnected in the synthesized design with Auto Calibration Auto and external IDELAYCTRL


On 7 Series devices, when using the MIPI D-PHY RX IP (Including the MIPI CSI-2 RX Subsystem) with Auto Calibration and external IDELAYCTRL, I can see in the synthesized design that the HS lanes are unconnected after the ISERDES.

How can I resolve this issue?


This is a known issue for MIPI D-PHY IP and MIPI CSI-2 RX Subsystems, which only affects 7 Series devices:

  • Vivado 2017.3 - Users can download the MIPI D-PHY IP and MIPI CSI-2 RX Subsystem patch from (Xilinx Answer 70195) to work around this issue.
  • Vivado 2017.4 - This issue is resolved in the MIPI D-PHY LogiCORE IP in Vivado 2017.4 and later.

Linked Answer Records

Master Answer Records

AR# 70196
Date 03/21/2018
Status Active
Type General Article
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