AR# 70221

LogiCORE IP AXI Video Direct Memory Access v6.3 - What are the throughput limitations of the VDMA?

Description

The AXI VDMA allows for independent clocking of each of the data interfaces. 

The throughput maximum is not as simple as calculating the throughput maximum of the AXI interfaces.

This Answer Record aims to give general calculations for each of the possible implementations.

Solution

The AXI VDMA can be clocked either in synchronous mode or asynchronous mode.

If the AXI VDMA is clocked in synchronous mode, all the AXI data buses are running the same speed, and there is no need for clock conversion.

This is the simplest case and your throughput maximum is calculated by the Common Clock multiplied by the smaller of the Stream or Memory Mapped bus widths. 

 

Synchronous mode:

If the Stream bus is smaller than the MM bus:

  • (Stream bus width * common clock)

If the Memory Mapped bus is smaller than the Stream bus: 

  • (MM bus width * common clock)

 

In Asynchronous mode, the clock conversion is done before the width conversion. 

That means that the destination bus now limits the bandwidth.

The equations to determine the bottleneck are listed by the equations below.

 

For Stream to Memory Mapped in Asynchronous Mode:

The MM clock is slower than the Stream clock and the Stream bus is larger than the MM bus:

  • (Stream bus width * MM clock)

The MM clock is slower than the Stream clock and the Stream bus is larger than the MM bus:

  • (MM bus width * MM clock)

The MM clock is faster than the Stream clock and the Stream bus is smaller than the MM bus:

  • (Stream bus width * Stream)

The MM clock is faster than the Stream clock and the Stream bus is larger than the MM bus:

  • (MM bus width * MM clock)

 

For Memory Mapped to Stream in Asynchronous Mode:

The Stream clock is slower than the MM clock and the Stream bus is larger than the MM bus:

  • (MM bus width * Stream clock)

The Stream clock is slower than the MM clock and the Stream bus is smaller than the MM bus:

  • (Stream bus width * Stream clock)

The Stream clock is faster than the MM clock and the Stream bus is smaller than the MM bus:

  • (MM bus width * MM clock)

The Stream clock is faster than the MM clock and the Stream bus is larger than the MM bus:

  • (Stream bus width * Stream clock)

 

Example 1:

Memory Mapped to Stream:

  • m_axi_mm2s_aclk = 200MHz and the data width = 32
  • m_axis_mm2s_aclk = 100MHz and the data width = 64

Each of these buses has the same maximum throughput of 6.4Gb/s but because the VDMA converts the clock before the data width, the maximum throughput of the VDMA is 3.2Gb/S.

  • (MM bus width * Stream clock) = (32*100MHz) = 3.2Gb/S

 

 Example 2:

Memory Mapped to Stream:

  • m_axi_mm2s_aclk = 100MHz and the data width = 64
  • m_axis_mm2s_aclk = 200MHz and the data width = 32

Each of these buses has the same maximum throughput of 6.4Gb/s and because the VDMA converts the clock before the data width, the maximum throughput of the VDMA is 6.4Gb/S.

  • (Stream bus width * Stream clock) = (200MHz * 32) = 6.4Gb/S

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AR# 70221
Date 01/22/2018
Status Active
Type General Article
IP