Xilinx has identified a case where the transceiver RX reset is triggered continuously preventing RXAUI core from finishing the reset sequence in UltraScale and UltraScale+ devices.
Version Found: RXAUI V4_4 in Vivado in 2017.2
Version Resolved: RXAUI v4_4 Rev 2 in Vivado in 2017.4
RXAUI core transceiver RX reset has a dependency on the synchronization completion of all the lanes based on a counter.
Reset done is not completing due to multiple resets given by the core based on the sync watchdog counter.
It is observed that the current 16 bit counter is not sufficient for CDR lock to be achieved in some cases.
To resolve the issue, increase the SYNC_COUNT_LENGTH to 26 from 16 in core name_block.v/vhd module in the core using (Xilinx Answer 57546)