This answer record contains the Release Notes and Known Issues for the UHD-SDI GT and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2017.3 and later.
UHD-SDI GT Page:
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version||IP Changelog||IP Patches||Standalone Software Driver Patches|
|v2.0 (Rev. 1)||2019.2||(Xilinx Answer 72923)||(Xilinx Answer 73173)|
|v2.0||2019.1||(Xilinx Answer 72242)||(Xilinx Answer 72474)|
|v1.0 (Rev 3)||2018.3||(Xilinx Answer 71806)||(Xilinx Answer 72075)|
|v1.0 (Rev. 2)||2018.2||(Xilinx Answer 71212)|
|v1.0 (Rev. 1)||2018.1||(Xilinx Answer 70699)||(Xilinx Answer 70974)|
|v1.0||2017.3||(Xilinx Answer 69903)|
The table below provides Answer Records for general guidance when using the UHD-SDI GT.
|Article Number||Article Title|
|(Xilinx Answer 72449)||UltraScale+ GTH/GTY - Why do I see link errors on the TX when using QPLL0 and QPLL1 to switch line rates on the RX between 11.88 Gbps and 11.88/1.001 Gbps?|
Known and Resolved Issues:
The following table provides known issues for UHD-SDI GT, starting with v1.0, initially released in Vivado 2017.3.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Article Number||Article Title||Version Found||Version Resolved|
|(Xilinx Answer 73216)||Why does synthesis fail in Vivado 2019.2 when the core is configured for HD-SDI, 3G-SDI or 6G-SDI?||v2.0 (Rev. 1)||N/A|
|(Xilinx Answer 73203)||Why do I receive a Synthesis error when enabling 4 lanes in Vivado 2019.2?||v2.0 (Rev. 1)||N/A|
|(Xilinx Answer 73174)||Switching between PICXO and FRACXO has no impact on the ports of the core in Vivado 2019.2||v2.0 (Rev. 1)||N/A|
|(Xilinx Answer 73044)||Why does synthesis fail in Vivado 2019.1 for -1LV UltraScale, UltraScale+ and Zynq MPSoC Devices?||v2.0||v2.0 (Rev. 1)|
|(Xilinx Answer 72575)||Why does synthesis fail when not using intf_0_qpll1_refclk_in?||v2.0||v2.0 (Rev. 1)|
|(Xilinx Answer 72516)||Why can the GTH and GTY not be selected on the XCKU15P-2FFVE1517I in Vivado 2019.1?||v2.0||v2.0 (Rev. 1)|
|(Xilinx Answer 72511)||Why is the port list different when selecting enable PICXO in GTY between Vivado 2018.3 and Vivado 2019.1?||v2.0||v2.0 (Rev. 1)|
|(Xilinx Answer 72108)||Only the first link is working in multi-link configuration||v1.0 (Rev 3)||N/A|
|(Xilinx Answer 70994)||Why does the UHD-SDI GT wrapper fail to implement when selecting a multi-link configuration?||v1.0 (Rev. 1)||v1.0 (Rev 2)|
|(Xilinx Answer 71055)||Why do I get Critical Warnings and Errors mentioning a cmp_gt_sts pin when trying to implement the UHD-SDI GT?||v1.0 (Rev. 1)||N/A|
|12/02/2019||Added (Xilinx Answer 73173) to version table and (Xilinx Answer 73216), (Xilinx Answer 73203), (Xilinx Answer 73174) to known issue table|
|11/07/2019||Added (Xilinx Answer 72923) to version table and (Xilinx Answer 73044) to known issues table|
|10/30/2019||Added v2.0 (Rev. 1) to Version Table|
|09/27/2019||Added (Xilinx Answer 72449)|
|07/26/2019||Added v2.0 to Version Table and (Xilinx Answer 72511), (Xilinx Answer 72516) and (Xilinx Answer 72575)|
|03/15/2019||Added v1.0 (Rev 3) to Version Table and (Xilinx Answer 72108)|
|10/09/2018||Added v1.0 (Rev. 2) to Version Table|
|04/23/2018||Added v1.0 (Rev. 1) to Version Table and (Xilinx Answer 71055) and (Xilinx Answer 70994)|