I am receiving the error below in my design which has a PL MIG with a second AXI interface for ECC register management:
To fix this issue, you will need to apply the attached patch.
The patch should be applied to <plnx-proj-root>/project-spec/meta-user/recipes-bsp/device-tree/device-tree-generation_%.bbappend
Note: To apply a patch to recipes, please refer to (UG1144) or http://www.wiki.xilinx.com/PetaLinux+Yocto+Tips
|Name||File Size||File Type|
|Boards & Kits||