General Description: When a design is synthesized in FPGA Express with the Preserve Hierarchy selected, multiple XNF files are generated -- one for each HDL module. Starting in Express 3.2, Express writes an NCF file for the timing constraints which are entered via the Express constraints GUI. The NCF may contain hierarchical path names for signals and instances in lower-level design modules that are constrained.
However, NGDBUILD reads this NCF file before it reads all the lower-level XNF files, any signals or instances which are in lower-level modules produce an error like:
ERROR:NgdHelpers:14 - Could not find INST(s) "MACHINE/current_state_reg<1>" in design "stopwatch". INST entry is "INST "MACHINE/current_state_reg<1>" TNM = "p0-To" ;
Two solutions exist:
1. Do not Preserve Hierarchy in FPGA Express. This will produce one flattened XNF file and NGDBUILD will have the complete design data before processing the NCF file.
2. Rename the NCF file to UCF. NGDBUILD will read all the XNF files and then process the UCF file. If you have an existing UCF file, you will need to merge the NCF and UCF into a single UCF file.