AR# 70324


DMA Subsystem for PCI Express (Vivado 2017.3/2017.4) - Tactical patch for issues fixes


Version Found: v4.0/v4.0 (Rev1)

Version Resolved and other Known Issues: (Xilinx Answer 65443)

The tactical patch provided in this answer record contains fixes for the following issues:
Issue 1:
If Max Read Request Size = 128B, MPS= 128B and transfer length= 129B are set, DMA transfer does not complete.
The following issues are seen:

  • For H2C transfer, two Read Requests are created and two completions returned but the second completion does not appear on the AXI bus.
  • For C2H transfer, s_axis_cc_tready is deasserted.

Issue 2:

  • H2C transfer hangs when the AXI data width is 128-bit and 64 bit addressing mode is enabled.

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express


For instruction on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.

Two separate patches for Vivado 2017.3 and 2017.4 are provided in this answer record. Please use the corresponding patch for the Vivado version you are using.

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

02/05/2018 - Initial Release


Associated Attachments

AR# 70324
Date 02/05/2018
Status Active
Type Known Issues
People Also Viewed