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AR# 70386

2017.4 Vivado IP Release Notes - All IP Change Log Information

Description

This Answer Record contains a comprehensive list of IP change log information from Vivado 2017.4 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

(c) Copyright 2018 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

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100M/1G TSN Subsystem (1.0)

* Version 1.0 (Rev. 1)

* General: No Functional Changes

* Revision change in one or more subcores

10G Ethernet MAC (15.1)

* Version 15.1 (Rev. 4)

* No changes

10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

* Version 6.0 (Rev. 11)

* Revision change in one or more subcores

10G Ethernet Subsystem (3.1)

* Version 3.1 (Rev. 7)

* Revision change in one or more subcores

10G/25G Ethernet Subsystem (2.3)

* Version 2.3 (Rev. 1)

* Feature Enhancement: Updated for CR

* Revision change in one or more subcores

1G/10G/25G Switching Ethernet Subsystem (1.0)

* Version 1.0 (Rev. 1)

* Feature Enhancement: Added device support for Virtex UltraScale GTH, Kintex UltraScale GTH, Kintex UltraScale+ GTH, Zynq UltraScale+ GTH

* Revision change in one or more subcores

1G/2.5G Ethernet PCS/PMA or SGMII (16.1)

* Version 16.1 (Rev. 2)

* Feature Enhancement: Added support for rxoutclk for 1588 ptp

* Other: Updated for timing fix

* Revision change in one or more subcores

32-bit Initiator/Target for PCI (7 Series) (5.0)

* Version 5.0 (Rev. 9)

* Fixed issue with the paid license where it timed out similar to the evaluation license.

3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 14)

* No changes

3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 13)

* No changes

3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 12)

* No changes

3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 15)

* General: Change to metadata. No change to functionality

3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 12)

* No changes

3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 13)

* No changes

40G/50G Ethernet Subsystem (2.3)

* Version 2.3 (Rev. 1)

* Feature Enhancement: CR

* Revision change in one or more subcores

64-bit Initiator/Target for PCI (7 Series) (5.0)

* Version 5.0 (Rev. 9)

* Fixed issue with the paid license where it timed out similar to the evaluation license.

7 Series FPGAs Transceivers Wizard (3.6)

* Version 3.6 (Rev. 8)

* Bug Fix: Fixed logic related to XAZU devices support

* Bug Fix: Fixed GUI to follow Zynq datasheet condition to not support 2 byte internal data width for line rates above 5.0 Gbps

* Bug Fix: Updated the DRC used for checking valid Reference Clock selection

7 Series Integrated Block for PCI Express (3.3)

* Version 3.3 (Rev. 7)

* General: Removed 'xx' in the Interface values

AHB-Lite to AXI Bridge (3.0)

* Version 3.0 (Rev. 13)

* Revision change in one or more subcores

AMM AXI Bridge (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

AXI 1G/2.5G Ethernet Subsystem (7.1)

* Version 7.1 (Rev. 2)

* General: Refer to tri_mode_ethernet_mac v9_0 and gig_ethernet_pcs_pma v16_1 core change logs for changes in the sub cores of this core

* General: Updated for dangling port fix

* Revision change in one or more subcores

AXI AHBLite Bridge (3.0)

* Version 3.0 (Rev. 13)

* Revision change in one or more subcores

AXI AMM Bridge (1.0)

* Version 1.0 (Rev. 5)

* Revision change in one or more subcores

AXI APB Bridge (3.0)

* Version 3.0 (Rev. 13)

* Revision change in one or more subcores

AXI BRAM Controller (4.0)

* Version 4.0 (Rev. 13)

* General: Modified Memory_Depth to support 64bit addressing

AXI Bridge for PCI Express Gen3 Subsystem (3.0)

* Version 3.0 (Rev. 5)

* Bug Fix: Fixed simulation parameter hierarchy when project is in VHDL language or when external Startup primitive is selected.

* Feature Enhancement: Added Tandem and PR simulation support for UltraScale devices

* Other: Changed IP example design simulation timeout value to 2.5ms

* Other: Removed 'xx' in the Interface values on PCIe ID GUI tab

* Revision change in one or more subcores

AXI CAN (5.0)

* Version 5.0 (Rev. 18)

* Revision change in one or more subcores

AXI Central Direct Memory Access (4.1)

* Version 4.1 (Rev. 15)

* Revision change in one or more subcores

AXI Chip2Chip Bridge (5.0)

* Version 5.0 (Rev. 1)

* Revision change in one or more subcores

AXI Clock Converter (2.1)

* Version 2.1 (Rev. 14)

* Revision change in one or more subcores

AXI Crossbar (2.1)

* Version 2.1 (Rev. 16)

* Revision change in one or more subcores

AXI Data FIFO (2.1)

* Version 2.1 (Rev. 14)

* Revision change in one or more subcores

AXI Data Width Converter (2.1)

* Version 2.1 (Rev. 15)

* Revision change in one or more subcores

AXI DataMover (5.1)

* Version 5.1 (Rev. 17)

* Revision change in one or more subcores

AXI Direct Memory Access (7.1)

* Version 7.1 (Rev. 16)

* General: Enhanced support for IP Integrator

* General: Updates to example design

* Revision change in one or more subcores

AXI EMC (3.0)

* Version 3.0 (Rev. 15)

* Revision change in one or more subcores

AXI EPC (2.0)

* Version 2.0 (Rev. 18)

* Revision change in one or more subcores

AXI Ethernet Buffer (2.0)

* Version 2.0 (Rev. 17)

* Revision change in one or more subcores

AXI Ethernet Clocking (2.0)

* Version 2.0 (Rev. 2)

* No changes

AXI EthernetLite (3.0)

* Version 3.0 (Rev. 13)

* Revision change in one or more subcores

AXI GPIO (2.0)

* Version 2.0 (Rev. 17)

* Revision change in one or more subcores

AXI HWICAP (3.0)

* Version 3.0 (Rev. 19)

* Revision change in one or more subcores

AXI IIC (2.0)

* Version 2.0 (Rev. 18)

* Revision change in one or more subcores

AXI Interconnect (2.1)

* Version 2.1 (Rev. 16)

* Revision change in one or more subcores

AXI Interrupt Controller (4.1)

* Version 4.1 (Rev. 10)

* No changes

AXI Lite IPIF (3.0)

* Version 3.0 (Rev. 4)

* No changes

AXI MMU (2.1)

* Version 2.1 (Rev. 13)

* Revision change in one or more subcores

AXI Master Burst (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI Memory Mapped To PCI Express (2.8)

* Version 2.8 (Rev. 7)

* Feature Enhancement: Added c_axibar_chk_slv_err option to enable Slave Error response when AXIBAR is missed

* Other: Added AXI register description in component.xml IP-XACT file

* Revision change in one or more subcores

AXI Memory Mapped to Stream Mapper (1.1)

* Version 1.1 (Rev. 14)

* Revision change in one or more subcores

AXI Multi Channel Direct Memory Access (1.0)

* Version 1.0 (Rev. 1)

* General: Bug fix

* Revision change in one or more subcores

AXI Performance Monitor (5.0)

* Version 5.0 (Rev. 17)

* Revision change in one or more subcores

AXI Protocol Checker (2.0)

* Version 2.0 (Rev. 1)

* General: pc_status is now optionally has mark_debug attribute controlled by hidden user_param enable_mark_debug

* General: Added has_wstrb parameter for metadata assertion checks

* Revision change in one or more subcores

AXI Protocol Converter (2.1)

* Version 2.1 (Rev. 15)

* Revision change in one or more subcores

AXI Protocol Firewall (1.0)

* Version 1.0 (Rev. 3)

* General: Added example design.

* Revision change in one or more subcores

AXI Quad SPI (3.2)

* Version 3.2 (Rev. 14)

* General: Updates to constraints. Relaxed the 1ns Max Delay to 1.3ns

* Revision change in one or more subcores

AXI Register Slice (2.1)

* Version 2.1 (Rev. 15)

* Bug Fix: Fixed sub-module instance names for SLR-crossing mode for easier manual floorplanning.

* New Feature: Added Multi-SLR-crossing mode with variable pipeline stages per SLR.

* Revision change in one or more subcores

AXI SmartConnect (1.0)

* Version 1.0 (Rev. 7)

* General: Minor internal change to facilitate testing.  No functional changes.

* Revision change in one or more subcores

AXI TFT Controller (2.0)

* Version 2.0 (Rev. 19)

* Revision change in one or more subcores

AXI Timebase Watchdog Timer (3.0)

* Version 3.0 (Rev. 7)

* Revision change in one or more subcores

AXI Timer (2.0)

* Version 2.0 (Rev. 17)

* Revision change in one or more subcores

AXI Traffic Generator (3.0)

* Version 3.0 (Rev. 1)

* General: Updates to example design TB

* Revision change in one or more subcores

AXI UART16550 (2.0)

* Version 2.0 (Rev. 17)

* Revision change in one or more subcores

AXI USB2 Device (5.0)

* Version 5.0 (Rev. 16)

* Revision change in one or more subcores

AXI Uartlite (2.0)

* Version 2.0 (Rev. 19)

* Revision change in one or more subcores

AXI Verification IP (1.1)

* Version 1.1 (Rev. 1)

* General: updated example design

* General: added slv_rd_driver verbosity

* General: modified interface assertion

* Revision change in one or more subcores

AXI Video Direct Memory Access (6.3)

* Version 6.3 (Rev. 3)

* Revision change in one or more subcores

AXI Virtual FIFO Controller (2.0)

* Version 2.0 (Rev. 17)

* Revision change in one or more subcores

AXI-Stream FIFO (4.1)

* Version 4.1 (Rev. 12)

* Revision change in one or more subcores

AXI4-Stream Accelerator Adapter (2.1)

* Version 2.1 (Rev. 12)

* No changes

AXI4-Stream Broadcaster (1.1)

* Version 1.1 (Rev. 15)

* Revision change in one or more subcores

AXI4-Stream Clock Converter (1.1)

* Version 1.1 (Rev. 16)

* Revision change in one or more subcores

AXI4-Stream Combiner (1.1)

* Version 1.1 (Rev. 14)

* Revision change in one or more subcores

AXI4-Stream Data FIFO (1.1)

* Version 1.1 (Rev. 16)

* Revision change in one or more subcores

AXI4-Stream Data Width Converter (1.1)

* Version 1.1 (Rev. 14)

* Revision change in one or more subcores

AXI4-Stream Interconnect (2.1)

* Version 2.1 (Rev. 16)

* Revision change in one or more subcores

AXI4-Stream Protocol Checker (1.2)

* Version 1.2 (Rev. 1)

* Revision change in one or more subcores

AXI4-Stream Register Slice (1.1)

* Version 1.1 (Rev. 15)

* Revision change in one or more subcores

AXI4-Stream Subset Converter (1.1)

* Version 1.1 (Rev. 15)

* Revision change in one or more subcores

AXI4-Stream Switch (1.1)

* Version 1.1 (Rev. 15)

* Revision change in one or more subcores

AXI4-Stream Verification IP (1.1)

* Version 1.1 (Rev. 1)

* General: update interface assertion

* Revision change in one or more subcores

AXI4-Stream to Video Out (4.0)

* Version 4.0 (Rev. 8)

* Revision change in one or more subcores

Accumulator (12.0)

* Version 12.0 (Rev. 11)

* No changes

Adder/Subtracter (12.0)

* Version 12.0 (Rev. 11)

* No changes

Aurora 64B66B (11.2)

* Version 11.2 (Rev. 3)

* Bug Fix: Fixed CDC warning for HLD_POLARITY_OUT signal.

* Revision change in one or more subcores

Aurora 8B10B (11.1)

* Version 11.1 (Rev. 3)

* General: Added support for CPG238 packages in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices

* Revision change in one or more subcores

Binary Counter (12.0)

* Version 12.0 (Rev. 11)

* No changes

Block Memory Generator (8.4)

* Version 8.4 (Rev. 1)

* General: Write depth shown in IP GUI is now dependent on number of BRAMs available in a chosen device, no functional changes

CANFD (1.0)

* Version 1.0 (Rev. 8)

* General: aSpartan7 device support added, no functional changes

* Revision change in one or more subcores

CIC Compiler (4.0)

* Version 4.0 (Rev. 12)

* No changes

CORDIC (6.0)

* Version 6.0 (Rev. 13)

* General: Add cstdlib include to run_bitacc_cmodel to allow correct compilation with later versions of GCC. No change to functionality.

CPRI (8.8)

* Version 8.8 (Rev. 1)

* Bug Fix: Fixed methodology TIMING-11 violations by removing redundant set_max_delay constraints.

* Bug Fix: Fixed bug in 7 Series logic which resulted in Vivado warnings.

* Bug Fix: Hard FEC now corrupts sync headers in the case of an uncorrected codeword iaw IEEE 802.3bj-2014 91.5.3.3.

* Bug Fix: Fixed bug in Hard FEC implementations where corrected_cw_inc was asserted on every codeword.

* Feature Enhancement: Disabled Slave option in GUI when Hard FEC is selected, slave is not currently supported with Hard FEC.

* Feature Enhancement: Optimized synchronization logic, removing Vivado methodology warnings.

* Feature Enhancement: Refactored TX control word logic to reduce low fan out control sets.

* Feature Enhancement: Updated get_pins constraints to improve run times.

* Feature Enhancement: Added false_path constraints to unused picoblaze ports to remove unconstrained internal endpoints warnings.

* Other: Added support for azynquplus devices.

* Revision change in one or more subcores

Chroma Resampler (4.0)

* Version 4.0 (Rev. 13)

* Revision change in one or more subcores

Clock Verification IP (1.0)

* Version 1.0

* No changes

Clocking Wizard (5.4)

* Version 5.4 (Rev. 3)

* Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL

* Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4 CR-991054

Color Correction Matrix (6.0)

* Version 6.0 (Rev. 14)

* Revision change in one or more subcores

Color Filter Array Interpolation (7.0)

* Version 7.0 (Rev. 13)

* Revision change in one or more subcores

Compact GT (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

Complex Multiplier (6.0)

* Version 6.0 (Rev. 14)

* General: Add cstdlib include to run_bitacc_cmodel to allow correct compilation with later versions of GCC. No change to functionality.

Concat (2.1)

* Version 2.1 (Rev. 1)

* No changes

Constant (1.1)

* Version 1.1 (Rev. 3)

* No changes

Convolution Encoder (9.0)

* Version 9.0 (Rev. 12)

* No changes

DDR3 SDRAM (MIG) (1.4)

* Version 1.4 (Rev. 3)

* Revision change in one or more subcores

DDR4 SDRAM (MIG) (2.2)

* Version 2.2 (Rev. 3)

* General: Updated for 2017.4

* Revision change in one or more subcores

DDS Compiler (6.0)

* Version 6.0 (Rev. 15)

* General: Add cstdlib include to run_bitacc_cmodel to allow correct compilation with later versions of GCC. No change to functionality.

DMA/Bridge Subsystem for PCI Express (PCIe) (4.0)

* Version 4.0 (Rev. 1)

* Bug Fix: Allow MSI-X Table and PBA registers to be programed while MSI-X Enable bit in MSIX Control register is 0. (Affects Bridge functional mode only)

* Bug Fix: Corrected MSI-X Table Size to 'h1F (32 vectors)

* Bug Fix: Corrected CC to TX conversion which was causing register read failures when there is high C2H traffic. (this issue affects both DMA and Bridge functional mode - 7 Series only)

* Bug Fix: Fixed the receive data for PCIe Hard Block when 64 bit addressing is enabled. (this issue affects both DMA and Bridge functional mode - 7 Series only)

* Bug Fix: Fixed ext_sys_clk_bufg option in UltraScale+

* Feature Enhancement: Added Auto RX Equalization support in the GT Settings GUI page.

* Revision change in one or more subcores

DSP48 Macro (3.0)

* Version 3.0 (Rev. 15)

* No changes

DUC/DDC Compiler (3.0)

* Version 3.0 (Rev. 13)

* General: Add cstdlib include to run_bitacc_cmodel to allow correct compilation with later versions of GCC. No change to functionality.

Debug Bridge (3.0)

* Version 3.0 (Rev. 1)

* General: Updated info message for GUI modes

Discrete Fourier Transform (4.0)

* Version 4.0 (Rev. 14)

* No changes

DisplayPort (7.0)

* Version 7.0 (Rev. 7)

* Revision change in one or more subcores

DisplayPort RX Subsystem (2.1)

* Version 2.1 (Rev. 1)

* Feature Enhancement: A7 device discontinued

* Revision change in one or more subcores

DisplayPort TX Subsystem (2.1)

* Version 2.1 (Rev. 1)

* Feature Enhancement: A7 device discontinued

* Revision change in one or more subcores

Distributed Memory Generator (8.0)

* Version 8.0 (Rev. 12)

* No changes

Divider Generator (5.1)

* Version 5.1 (Rev. 12)

* No changes

Double Data Rate Sampling (1.0)

* Version 1.0

* No changes

ECC (2.0)

* Version 2.0 (Rev. 12)

* No changes

Ethernet PHY MII to Reduced MII (2.0)

* Version 2.0 (Rev. 17)

* Revision change in one or more subcores

FEC 5G Common Utilities (1.0)

* Version 1.0

* No changes

FIFO Generator (13.2)

* Version 13.2 (Rev. 1)

* Revision change in one or more subcores

FIR Compiler (7.2)

* Version 7.2 (Rev. 10)

* Feature Enhancement: Add option to remove shift register inference attributes; SHREG_EXTRACT and SRL_STYLE

Fast Fourier Transform (9.0)

* Version 9.0 (Rev. 14)

* General: Clock frequency improvement for floating point FFT.  No change in functionality.

* General: Bugfix in C model to resolve data-dependent incorrect block exponent when modelling the Pipelined, Streaming I/O architecture with a Block Floating Point datapath.

* Revision change in one or more subcores

Fiber Channel 32GFC RS-FEC (1.0)

* Version 1.0 (Rev. 5)

* Revision change in one or more subcores

Fixed Interval Timer (2.0)

* Version 2.0 (Rev. 8)

* No changes

FlexO 100G RS-FEC (1.0)

* Version 1.0 (Rev. 5)

* General: No functional changes.

* Revision change in one or more subcores

Floating-point (7.1)

* Version 7.1 (Rev. 5)

* No changes

G.709 FEC Encoder/Decoder (2.3)

* Version 2.3 (Rev. 1)

* No changes

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

* Version 1.0 (Rev. 14)

* No changes

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

* Version 2.0 (Rev. 16)

* General: Update source code comments, no change to functionality.

Gamma Correction (7.0)

* Version 7.0 (Rev. 14)

* Revision change in one or more subcores

Gamma LUT (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

Gmii to Rgmii (4.0)

* Version 4.0 (Rev. 5)

* General: Adding support for automotive Zynq UltraScale+ devices

HDCP (1.0)

* Version 1.0 (Rev. 3)

* No changes

HDCP 2.2 Cipher (1.0)

* Version 1.0 (Rev. 2)

* No changes

HDCP 2.2 Montgomery Modular Multiplier (1.0)

* Version 1.0 (Rev. 2)

* No changes

HDCP 2.2 Random Number Generator (1.0)

* Version 1.0 (Rev. 1)

* No changes

HDCP 2.2 Receiver (1.0)

* Version 1.0 (Rev. 6)

* No changes

HDCP 2.2 Transmitter (1.0)

* Version 1.0 (Rev. 6)

* No changes

HDMI 1.4/2.0 Receiver (3.0)

* Version 1.1

* No changes

HDMI 1.4/2.0 Receiver Subsystem (3.0)

* Version 3.0 (Rev. 1)

* Bug Fix: Fixed incorrect HFP and HBP value for VIC106

* Bug Fix: Allow axi4-lite to read Aud_Reset and TMDSClkRatio registers bits

* Bug Fix: Fixed HBR Audio support issue

* Bug Fix: Fixed Audio Channel Swapping issue in Audio Pattern Generator

* Bug Fix: Fixed issue in PS settings to support FSBL

HDMI 1.4/2.0 Transmitter (3.0)

* Version 2.0

* No changes

HDMI 1.4/2.0 Transmitter Subsystem (3.0)

* Version 3.0 (Rev. 1)

* Bug Fix: Allow axi4-lite to read Aud_Reset and TMDSClkRatio registers bits

* Bug Fix: Fixed HBR Audio support issue

* Bug Fix: Fixed Audio Channel Swapping issue in Audio Pattern Generator

* Bug Fix: Fixed DDC issue on simultaneously rising of SCL and SDA signals

* Bug Fix: Fixed issue in PS settings to support FSBL

High Speed SelectIO Wizard (3.2)

* Version 3.2 (Rev. 3)

* Bug Fix: Fixed issue in DIFF_TERM selection for LVDS standard

* Feature Enhancement: Updated support for Asynchronous Mode (Beta)

* Other: Asynchronous Mode (Beta) support is enabled for "Rx Only" Bus Direction

IBERT 7 Series GTH (3.0)

* Version 3.0 (Rev. 16)

* No changes

IBERT 7 Series GTP (3.0)

* Version 3.0 (Rev. 16)

* No changes

IBERT 7 Series GTX (3.0)

* Version 3.0 (Rev. 16)

* No changes

IBERT 7 Series GTZ (3.1)

* Version 3.1 (Rev. 14)

* Revision change in one or more subcores

IBERT UltraScale GTH (1.3)

* Version 1.3 (Rev. 9)

* General: Updated respective device family to production.

* Revision change in one or more subcores

IBERT UltraScale GTY (1.2)

* Version 1.2 (Rev. 9)

* General: Added device support for Virtex UltraScale+ HBM devices.

* Revision change in one or more subcores

IEEE 802.3 200G RS-FEC (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

IEEE 802.3 25G RS-FEC (1.0)

* Version 1.0 (Rev. 7)

* Revision change in one or more subcores

IEEE 802.3 400G RS-FEC (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

IEEE 802.3 50G RS-FEC (1.0)

* Version 1.0 (Rev. 7)

* Revision change in one or more subcores

IEEE 802.3bj 100G RS-FEC (1.0)

* Version 1.0 (Rev. 11)

* Revision change in one or more subcores

ILA (Integrated Logic Analyzer) (6.2)

* Version 6.2 (Rev. 5)

* General: Updated ILA to handle XDC warnings

IOModule (3.1)

* Version 3.1 (Rev. 3)

* General: Provide RTL implementation of PIT counter, no functional changes

Image Enhancement (8.0)

* Version 8.0 (Rev. 14)

* Revision change in one or more subcores

In System IBERT (1.0)

* Version 1.0 (Rev. 5)

* Revision change in one or more subcores

Interlaken 150G (2.3)

* Version 2.3 (Rev. 1)

* Revision change in one or more subcores

Interleaver/De-interleaver (8.0)

* Version 8.0 (Rev. 11)

* No changes

JESD204 (7.2)

* Version 7.2 (Rev. 1)

* Bug Fix: Fixed issue stopping the user from choosing the GT type with Zynq UltraScale Plus devices in ffvd1760 package

* Revision change in one or more subcores

JESD204 PHY (4.0)

* Version 4.0 (Rev. 1)

* Bug Fix: Fixed issue causing CPLL reset pulse period to be too short in certain configurations AR70023

* Bug Fix: Fixed issue stopping the user from choosing the GT type with Zynq UltraScale Plus devices in ffvd1760 package

* Revision change in one or more subcores

JESD204C (2.0)

* Version 2.0 (Rev. 1)

* Revision change in one or more subcores

JTAG to AXI Master (1.2)

* Version 1.2 (Rev. 5)

* Revision change in one or more subcores

LDPC Encoder/Decoder (1.0)

* Version 1.0 (Rev. 1)

* Bug Fix: Fixed layer look-up issue that result in incorrect DOUT data and parity flag for single block: See (Xilinx Answer 69966) 

LMB BRAM Controller (4.0)

* Version 4.0 (Rev. 14)

* General: Improved ECC timing when using more than one LMB port

LPDDR3 SDRAM (MIG) (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

LTE DL Channel Encoder (3.0)

* Version 3.0 (Rev. 13)

* No changes

LTE Fast Fourier Transform (2.0)

* Version 2.0 (Rev. 15)

* Revision change in one or more subcores

LTE PUCCH Receiver (2.0)

* Version 2.0 (Rev. 13)

* Revision change in one or more subcores

LTE RACH Detector (3.1)

* Version 3.1 (Rev. 1)

* General: Non-Functional correction to remove issue in evaluation core.

* Revision change in one or more subcores

LTE UL Channel Decoder (4.0)

* Version 4.0 (Rev. 13)

* No changes

Local Memory Bus (LMB) 1.0 (3.0)

* Version 3.0 (Rev. 9)

* No changes

MIPI CSI-2 Rx Controller (1.0)

* Version 1.0 (Rev. 7)

* Revision change in one or more subcores

MIPI CSI-2 Rx Subsystem (3.0)

* Version 3.0 (Rev. 1)

* Port Change: Added dlyctrl_rdy_in port when C_SHARE_IDLYCTRL set to false

* Feature Enhancement: Support for  Virtex-7, Kintex-7, Artix-7, Zynq-7000 devices at Production status

* Revision change in one or more subcores

MIPI CSI-2 Tx Controller (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

MIPI CSI-2 Tx Subsystem (2.0)

* Version 2.0 (Rev. 1)

* Feature Enhancement: Support for  Virtex-7, Kintex-7, Artix-7, Zynq-7000 devices at Production status

* Revision change in one or more subcores

MIPI D-PHY (4.0)

* Version 4.0 (Rev. 1)

* Port Change: Added dlyctrl_rdy_in port when C_SHARE_IDLYCTRL set to false

* Bug Fix: Fixed treadyhs assertion across lanes in D-PHY TX

* Bug Fix: HS_PREPARE duration fixed to be within specification limits for 7 Series MIPI D-PHY TX with OBUFTDS enabled

* Bug Fix: Fixed HS_SETTLE register value not getting updated in D-PHY RX

* Feature Enhancement: Support for  Virtex-7, Kintex-7, Artix-7, Zynq-7000 devices at Production status

* Other: Updated HSSIO DIFFERENTIAL_IO_TERMINATION parameter from NONE to TERM_NONE

* Revision change in one or more subcores

MIPI DSI Tx Controller (1.0)

* Version 1.0 (Rev. 5)

* Revision change in one or more subcores

MIPI DSI Tx Subsystem (2.0)

* Version 2.0 (Rev. 1)

* Feature Enhancement: Support for  Virtex-7, Kintex-7, Artix-7, Zynq-7000 devices at Production status

* Revision change in one or more subcores

Mailbox (2.1)

* Version 2.1 (Rev. 8)

* No changes

Memory Helper Core (1.4)

* Version 1.4

* No changes

Memory Interface Generator (MIG 7 Series) (4.0)

* Version 4.0 (Rev. 5)

* No changes

MicroBlaze (10.0)

* Version 10.0 (Rev. 5)

* Bug Fix: Prevent potential spurious software breakpoints. Versions that have this issue: 10.0. Can only occur with frequency optimization when debugging with software breakpoints.

* Bug Fix: Ensure that DZO bit in MSR is not inadvertently cleared. Versions that have this issue: 10.0. Can only occur with frequency optimization when using integer divide.

* Other: Generate warning if no cacheable memory is available when caches are enabled.

* Other: Add additional constraints for debug external trace.

MicroBlaze Debug Module (MDM) (3.2)

* Version 3.2 (Rev. 12)

* Bug Fix: Do not inactivate "Enable Cross Trigger" and "External Trace" when MDM is instantiated

* Feature Enhancement: Ensure that the MDM always responds to accesses on the AXI slave interface

* Feature Enhancement: Provide parameter to set external trigger reset value

* Feature Enhancement: Add alternate external trace protocol

MicroBlaze MCS (3.0)

* Version 3.0 (Rev. 7)

* Bug Fix: Propagate clock, reset and external interrupt properties from ports in IP Integrator block designs, and remove corresponding settings from the IP configuration dialog

* Other: Added support for XA Zynq UltraScale+ and XA Spartan-7 devices

* Revision change in one or more subcores

Multiplier (12.0)

* Version 12.0 (Rev. 13)

* No changes

Multiply Adder (3.0)

* Version 3.0 (Rev. 11)

* No changes

Mutex (2.1)

* Version 2.1 (Rev. 8)

* No changes

PCIe PHY IP (1.0)

* Version 1.0 (Rev. 7)

* Feature Enhancement: Update in asynchronous clock constraints

* Revision change in one or more subcores

Partial Reconfiguration Controller (1.2)

* Version 1.2 (Rev. 1)

* Bug Fix: Fixed the core in the IES/ncsim export_simulation flow

Partial Reconfiguration Decoupler (1.0)

* Version 1.0 (Rev. 5)

* No changes

Peak Cancellation Crest Factor Reduction (6.1)

* Version 6.1 (Rev. 2)

* No changes

Processor System Reset (5.0)

* Version 5.0 (Rev. 12)

* No changes

QDRII+ SRAM (MIG) (1.4)

* Version 1.4 (Rev. 3)

* General: Updated for 2017.4

* Revision change in one or more subcores

QDRIV SRAM (MIG) (2.0)

* Version 2.0 (Rev. 3)

* Revision change in one or more subcores

QDRIV SRAM PHY IP (2.0)

* Version 1.2

* No changes

QSGMII (3.4)

* Version 3.4 (Rev. 2)

* Bug Fix: Added enabling signals for data valid generation targeting 7 Series transceivers

* Revision change in one or more subcores

RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 11)

* No changes

RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 12)

* Revision change in one or more subcores

RLDRAM3 (MIG) (1.4)

* Version 1.4 (Rev. 3)

* General: Updated for 2017.4

* Revision change in one or more subcores

RXAUI (4.4)

* Version 4.4 (Rev. 2)

* Bug Fix: Changed value of SYNC_COUNT_LENGTH to 26 for UltraScale devices

* Revision change in one or more subcores

Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 13)

* No changes

Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 12)

* No changes

Reset Verification IP (1.0)

* Version 1.0

* No changes

S/PDIF (2.0)

* Version 2.0 (Rev. 18)

* Revision change in one or more subcores

SC EXIT (1.0)

* Version 1.0 (Rev. 6)

* General: Initialize memory to avoid VCD comparison failures

SC MMU (1.0)

* Version 1.0 (Rev. 5)

* No changes

SC SI_CONVERTER (1.0)

* Version 1.0 (Rev. 5)

* No changes

SC SPLITTER (1.0)

* Version 1.0 (Rev. 2)

* No changes

SC TRANSACTION_REGULATOR (1.0)

* Version 1.0 (Rev. 6)

* No changes

SDI RX to Video Bridge (2.0)

* Version 2.0

* No changes

SMPTE SD/HD/3G-SDI (3.0)

* Version 3.0 (Rev. 8)

* No changes

SMPTE UHD-SDI (1.0)

* Version 1.0 (Rev. 5)

* No changes

SMPTE UHD-SDI RX (1.0)

* Version 1.0

* No changes

SMPTE UHD-SDI RX SUBSYSTEM (1.0)

* Version 1.0 (Rev. 1)

* Bug Fix: Removed ZCU106 board reference from UHD-SDI Pass Through example design generation script

SMPTE UHD-SDI TX (1.0)

* Version 1.0

* No changes

SMPTE UHD-SDI TX SUBSYSTEM (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

SPI-4.2 (13.0)

* Version 13.0 (Rev. 11)

* No changes

SelectIO Interface Wizard (5.1)

* Version 5.1 (Rev. 10)

* General: ASPARTAN7 device support added

Sensor Demosaic (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

Serial RapidIO Gen2 (4.1)

* Version 4.1 (Rev. 2)

* Revision change in one or more subcores

SmartConnect AXI2SC Bridge (1.0)

* Version 1.0 (Rev. 5)

* No changes

SmartConnect Node (1.0)

* Version 1.0 (Rev. 7)

* Bug Fix: Add output flop on BRAM FIFO when in multiclock mode.

SmartConnect SC2AXI Bridge (1.0)

* Version 1.0 (Rev. 5)

* No changes

SmartConnect Switchboard (1.0)

* Version 1.0 (Rev. 4)

* No changes

Soft Error Mitigation (4.1)

* Version 4.1 (Rev. 10)

* No changes

Switch Core Top (1.0)

* Version 1.0 (Rev. 4)

* Revision change in one or more subcores

System Cache (4.0)

* Version 4.0 (Rev. 3)

* No changes

System ILA (1.1)

* Version 1.1 (Rev. 1)

* General: Updated IP based on AXI Protocol checker changes

* Revision change in one or more subcores

System Management Wizard (1.3)

* Version 1.3 (Rev. 6)

* No changes

TMR Comparator (1.0)

* Version 1.0 (Rev. 1)

* No changes

TMR Inject (1.0)

* Version 1.0 (Rev. 1)

* No changes

TMR Manager (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Corrected example design testbench port names to match generated wrapper

TMR Soft Error Mitigation Interface (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

TMR Voter (1.0)

* Version 1.0 (Rev. 1)

* No changes

TSN Tri Mode Ethernet MAC (1.0)

* Version 1.0 (Rev. 2)

* No changes

Timer Sync 1588 (1.2)

* Version 1.2 (Rev. 4)

* No changes

Tri Mode Ethernet MAC (9.0)

* Version 9.0 (Rev. 10)

* Bug Fix: Fixed bug in AVB RTC clock logic which resulted in the RTC clock second and nano-second fields being out of sync when the nano-second field rolled over

UHD-SDI GT (1.0)

* Version 1.0

* No changes

UltraScale 100G Ethernet Subsystem (2.3)

* Version 2.3 (Rev. 1)

* General: Updated for timing fix

* Revision change in one or more subcores

UltraScale FPGA Gen3 Integrated Block for PCI Express (4.4)

* Version 4.4 (Rev. 1)

* General: Removed GUI option for RBAR Capability because it is not supported in the core.

* General: Fixed pipe mode simulation issue when pipe line stages set to 2

* General: Changed Link Number (cfg_ds_port_number) in RP mode example design from 8'h9F to 8'h00

* Revision change in one or more subcores

UltraScale FPGAs Transceivers Wizard (1.7)

* Version 1.7 (Rev. 2)

* General: Updated the status of some transceiver configuration presets

* General: Modified delay powergood logic for GTHE4/GTYE4 to reduce warnings

UltraScale Soft Error Mitigation (3.1)

* Version 3.1 (Rev. 6)

* General: Update UltraScale+ IP status to production in alignment with speed file status

UltraScale+ 100G Ethernet Subsystem (2.4)

* Version 2.4 (Rev. 1)

* General: Added new Virtex UltraScale+ devices support

* Revision change in one or more subcores

UltraScale+ PCI Express 4c Integrated Block (1.0)

* Version 1.0 (Rev. 1)

* Feature Enhancement: Added Auto Rx Equalization support in the GT Settings GUI page.

* Feature Enhancement: added cfg_interrupt_msi_function_number in pcie4_cfg_external_msix interface.

* Feature Enhancement: Removed naming of the set_clock_groups in the IP level XDC.

* Feature Enhancement: Removed naming of the create_clock constraints in the IP level XDC.

* Feature Enhancement: Added clock_delay_group constraints in 512-I/F to fix timing.

* Revision change in one or more subcores

UltraScale+ PCI Express Integrated Block (1.3)

* Version 1.3 (Rev. 1)

* Feature Enhancement: Added Auto Rx Equalization support in the GT Settings GUI page.

* Feature Enhancement: Removed naming of the set_clock_groups in the IP level XDC.

* Feature Enhancement: Removed naming of the create_clock constraints in the IP level XDC.

* Feature Enhancement: Added clock_delay_group constraints in 512-I/F to fix timing.

* Other: Changed Link Number (cfg_ds_port_number) in RP mode example design from 8'h9F to 8'h00

* Revision change in one or more subcores

Universal Serial XGMII Ethernet Subsystem (1.0)

* Version 1.0 (Rev. 1)

* Bug Fix: In the example design AXI4-Lite FSM, block_lock checks are validated with gt_reset_done

* Other: Core marked as production

* Revision change in one or more subcores

Utility Reduced Logic (2.0)

* Version 2.0 (Rev. 3)

* No changes

Utility Vector Logic (2.0)

* Version 2.0 (Rev. 1)

* No changes

VIO (Virtual Input/Output) (3.0)

* Version 3.0 (Rev. 17)

* No changes

Video Color Space Conversion and Correction (1.0)

* Version 1.0 (Rev. 9)

* Revision change in one or more subcores

Video Deinterlacer (5.0)

* Version 5.0 (Rev. 9)

* Revision change in one or more subcores

Video Frame Buffer Read (2.0)

* Version 2.0 (Rev. 1)

* Revision change in one or more subcores

Video Frame Buffer Write (2.0)

* Version 2.0 (Rev. 1)

* Revision change in one or more subcores

Video Horizontal Chroma Resampler (1.0)

* Version 1.0 (Rev. 9)

* Revision change in one or more subcores

Video Horizontal Scaler (1.0)

* Version 1.0 (Rev. 9)

* Revision change in one or more subcores

Video In to AXI4-Stream (4.0)

* Version 4.0 (Rev. 7)

* No changes

Video Letterbox Engine (1.0)

* Version 1.0 (Rev. 9)

* Revision change in one or more subcores

Video Mixer (2.0)

* Version 2.0 (Rev. 1)

* General: Auto-assign address in simulation example design

* Revision change in one or more subcores

Video On Screen Display (6.0)

* Version 6.0 (Rev. 15)

* Revision change in one or more subcores

Video PHY Controller (2.1)

* Version 2.1 (Rev. 1)

* General: Added 8.1Gbps maximum GT line rate support for DP protocol in GTHE3 and GTHE4

Video Processing Subsystem (2.0)

* Version 2.0 (Rev. 7)

* Revision change in one or more subcores

Video Test Pattern Generator (7.0)

* Version 7.0 (Rev. 9)

* Revision change in one or more subcores

Video Timing Controller (6.1)

* Version 6.1 (Rev. 12)

* General: Added validation checks to customization GUI.

Video Vertical Chroma Resampler (1.0)

* Version 1.0 (Rev. 9)

* Revision change in one or more subcores

Video Vertical Scaler (1.0)

* Version 1.0 (Rev. 9)

* Revision change in one or more subcores

Video to SDI TX Bridge (2.0)

* Version 2.0

* No changes

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.3)

* Version 4.3 (Rev. 1)

* General: Removed GUI option for RBAR Capability since it is not supported in the core.

Viterbi Decoder (9.1)

* Version 9.1 (Rev. 8)

* No changes

XADC Wizard (3.3)

* Version 3.3 (Rev. 5)

* General: Added aspartan7 support for this IP

XAUI (12.3)

* Version 12.3 (Rev. 2)

* General: Added constraint in example design XDC file to prevent placement of IOs at HDIO locations

* Revision change in one or more subcores

XHMC (1.0)

* Version 1.0 (Rev. 5)

* Bug Fix: Correction in gt_drp address width for UltraScale+ GTH

* Bug Fix: Correction in isi_gt_txdiffctrl_in width for UltraScale+ GTH

* Bug Fix: Fixed RID width for non-reordering mode

* Revision change in one or more subcores

YCrCb to RGB Color-Space Converter (7.1)

* Version 7.1 (Rev. 12)

* Revision change in one or more subcores

ZYNQ UltraScale+ VCU (1.0)

* Version 1.0

* No changes

ZYNQ7 Processing System (5.5)

* Version 5.5 (Rev. 6)

* No changes

ZYNQ7 Processing System VIP (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

ZYNQMPSOC Processing System VIP (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

Zynq UltraScale+ MPSoC (3.1)

* Version 3.1 (Rev. 1)

* Bug Fix: Axi_vip wrapper issues on ACP port,S_AXI0_HP0_FPD port.

* Bug Fix: Issues with constraints generation in SDx runs.

* Bug Fix: Resolved Propagation of USER strength parameter PSU__M_AXI_GP2__FREQMHZ  during upgrade

* Revision change in one or more subcores

axi_msg (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

axi_sg (4.1)

* Version 4.1 (Rev. 8)

* Revision change in one or more subcores

interrupt_controller (3.1)

* Version 3.1 (Rev. 4)

* No changes

lib_bmg (1.0)

* Version 1.0 (Rev. 10)

* Revision change in one or more subcores

lib_cdc (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_fifo (1.0)

* Version 1.0 (Rev. 10)

* Revision change in one or more subcores

lib_pkg (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_srl_fifo (1.0)

* Version 1.0 (Rev. 2)

* No changes

 

AR# 70386
Date 01/17/2018
Status Active
Type Release Notes
Tools
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