Why do I see synthesis failures when using a Windows OS for synthesis?
When synthesizing a design including a TPG or a VPSS on windows, I get a synthesis error related to the AXI4-Stream interface:
[Synth 8-448] named port connection 's_axis_video_TVALID' does not exist for instance 'inst' of module 'bd_12f8_csc_0_v_csc' ["g:/ex/v_proc_ss_0_ex.srcs/sources_1/bd/vps_ex/ip/vps_ex_v_proc_ss_0_0/bd_0/ip/ip_6/synth/bd_12f8_csc_0.v":205]
What is the reason for this issue?
This is a known issue with the Vivado HLS compiler on Windows (the TPG and VPSS are HLS-based IPs).
The first thing that users should always attempt when synthesizing designs that contain HLS Based IP such as the TPG or VPSS is to reduce the path as much as possible.
In additional there are some patches that can also help work around these issues in some cases.
Answer Number | Answer Title | Version Found | Version Resolved |
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70182 | 2017.3 IP Flows - Synthesis fails on Video Mixer IP in Block Design; "Synthesis target needs to be generated before calling compile_c." | N/A | N/A |
70445 | 2017.4 Vivado HLS - Windows OS - Missing ports in the generated RTL when using hls::stream interfaces | N/A | N/A |
AR# 70421 | |
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Date | 04/25/2018 |
Status | Active |
Type | General Article |
Tools | |
IP |