2. Support
  3. AR# 7042: Foundation 2.1i: Missing speed grades for CPLD devices.
  4. AR# 70421: LogiCORE IP Test Pattern Generator (TPG) and LogiCORE IP Video Processing Subsystem (VPSS) - Why do I see synthesis failures when using a Windows OS for synthesis?

AR# 70421

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LogiCORE IP Test Pattern Generator (TPG) and LogiCORE IP Video Processing Subsystem (VPSS) - Why do I see synthesis failures when using a Windows OS for synthesis?

Description

Why do I see synthesis failures when using a Windows OS for synthesis?

When synthesizing a design including a TPG or a VPSS on windows, I get a synthesis error related to the AXI4-Stream interface:

[Synth 8-448] named port connection 's_axis_video_TVALID' does not exist for instance 'inst' of module 'bd_12f8_csc_0_v_csc' ["g:/ex/v_proc_ss_0_ex.srcs/sources_1/bd/vps_ex/ip/vps_ex_v_proc_ss_0_0/bd_0/ip/ip_6/synth/bd_12f8_csc_0.v":205]

What is the reason for this issue?

Solution

This is a known issue with the Vivado HLS compiler on Windows (the TPG and VPSS are HLS-based IPs).

The first thing that users should always attempt when synthesizing designs that contain HLS Based IP such as the TPG or VPSS is to reduce the path as much as possible.

  • i.e. Make the project name as short as possible, and place it in the shortest possible path (C:\x).
  • See also (Xilinx Answer 52787).

In additional there are some patches that can also help work around these issues in some cases.

  • Vivado 2017.3 - Users should update to Vivado 2018.1.
  • Vivado 2017.4 - Users can download a patch from (Xilinx Answer 70445) to work around the issue.
  • Vivado 2018.1 - This issue is fixed in 2018.1

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
65449 LogiCORE IP Video Processing Subsystem(VPSS) - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A
54536 LogiCORE IP Test Pattern Generator (TPG) - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
66753 LogiCORE Video Mixer - Release Notes and Known Issues for the Vivado 2016.1 tool and later versions N/A N/A
68764 LogiCORE Video Frame Buffer Read - Release Notes and Known Issues for the Vivado 2017.1 tool and later versions N/A N/A
68765 LogiCORE Video Frame Buffer Write - Release Notes and Known Issues for the Vivado 2017.1 tool and later versions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
70182 2017.3 IP Flows - Synthesis fails on Video Mixer IP in Block Design; "Synthesis target needs to be generated before calling compile_c." N/A N/A
70445 2017.4 Vivado HLS - Windows OS - Missing ports in the generated RTL when using hls::stream interfaces N/A N/A
AR# 70421
Date 04/25/2018
Status Active
Type General Article
Tools
IP
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